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    • 31. 发明授权
    • Subsampling communication receiver architecture with relaxed IFA readout timing
    • 采用宽松的IFA读出时序对通信接收机架构进行采样
    • US06963732B2
    • 2005-11-08
    • US10132436
    • 2002-04-25
    • Khurram MuhammadDirk Leipold
    • Khurram MuhammadDirk Leipold
    • H03H15/00H03H19/00H04B1/28H04B1/707H04L27/24H04B1/00
    • H03H15/00H03H19/004H04B1/0003H04B1/0025H04B1/28H04L27/24
    • A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform, and are also manipulated to implement a filtering operation such that the second voltage waveform represents a downconverted, filtered version of the first voltage waveform. The second waveform is driven by an amplifier stage (25), and the second waveform can be advantageously constructed so as to permit the amplifier stage to perform internal resets, offset corrections and other ancillary amplifier stage adjustments without losing information in the first waveform.
    • 第一周期性电压波形(20)被下变频成第二周期性电压波形(35,36)。 获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本(SA 1,SA 2 ...)。 将样本组合以产生第二电压波形,并且还被操纵以实现滤波操作,使得第二电压波形表示第一电压波形的下变换的滤波版本。 第二波形由放大器级(25)驱动,并且第二波形可以有利地构造成允许放大器级执行内部复位,偏移校正和其它辅助放大器级调整,而不会丢失第一波形中的信息。
    • 35. 发明授权
    • Digital, down-converted RF residual leakage signal mitigating RF residual leakage
    • 数字,降频转换的RF残留泄漏信号可减轻RF残留泄漏
    • US07706755B2
    • 2010-04-27
    • US11270121
    • 2005-11-09
    • Khurram MuhammadDirk Leipold
    • Khurram MuhammadDirk Leipold
    • H04B1/40
    • H03C5/00H04B1/525H04B1/707
    • The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.
    • 本发明提供了一种与全双工无线收发器一起使用的RF传输泄漏缓解器。 在一个实施例中,RF传输泄漏减轻器包括反相发生器,其被配置为将干扰收发器RF传输的RF发射反转信号提供给收发器的接收部分,从而产生残余泄漏信号。 此外,RF传输泄漏缓解器还包括耦合到反向发生器并被配置为基于将剩余泄漏信号减小到指定电平来调整干扰收发器RF传输的RF发射反转信号的残余处理器。
    • 39. 发明授权
    • Wireless communications device having type-II all-digital phase-locked loop (PLL)
    • 具有II型全数字锁相环(PLL)的无线通信设备
    • US07463873B2
    • 2008-12-09
    • US11122670
    • 2005-05-04
    • Robert B. StaszewskiDirk LeipoldKhurram Muhammad
    • Robert B. StaszewskiDirk LeipoldKhurram Muhammad
    • H03L7/093
    • H03L7/1075H03F1/0211H03F1/3282H03L7/093H03L7/0991H03L7/107H03L2207/50
    • System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115 ) and an integral loop gain block (integral loop gain block 1120 ). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the intergral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
    • 用于提供具有快速信号采集模式的II型(和更高阶)锁相环(PLL)的系统和方法。 优选实施例包括具有带有比例环路增益路径(比例环路增益电路1115)和积分环路增益块(积分环路增益块1120)的环路滤波器的无线通信设备。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽,从而快速获取所需信号的信号。 然后,在PLL的信号跟踪阶段期间,使用积分环路增益模块,并将其输出与比例环路增益路径的输出相结合,以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量,以帮助改善信号跟踪稳定时间。