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31. 发明授权

US08245104B2 Systems and methods for queue based data detection and decoding 有权
标题翻译：基于队列的数据检测和解码的系统和方法
公开(公告)号：US08245104B2
公开(公告)日：2012-08-14
申请号：US12114462
申请日：2008-05-02
申请人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
发明人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/2987 , G11B20/18 , G11B2020/185 , G11B2220/2516 , H03M13/09 , H03M13/1102 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6337 , H04L1/005 , H04L1/0057 , H04L1/0065
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括至少第一检测器，第二检测器，解码器和排队缓冲器的可变迭代数据处理系统。第一检测器可操作以在第一时间对输入数据集执行数据检测。解码器接收来自第一检测器的输出的导出并执行解码处理。在解码过程不能收敛的情况下，解码器输出被传送到第二检测器用于随后的检测和解码过程。

32. 发明授权

US08245061B2 Systems and methods for operational power management utilizing power islands 有权
标题翻译：利用电力岛进行电力管理的系统和方法
公开(公告)号：US08245061B2
公开(公告)日：2012-08-14
申请号：US12772108
申请日：2010-04-30
申请人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
发明人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/04 , G06F1/24 , G06F1/3268 , Y02D10/154
摘要： Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management controller. The power management controller is operable to apply power to one of the clock sources and to select another of the clock sources for synchronization of the circuit. Then, upon stabilization of the first clock source, it is selected by the power management controller to synchronize the circuit.
摘要翻译：本文公开了用于电力管理的各种系统和方法。例如，公开了包括两个或更多个时钟源和电源管理控制器的同步半导体电路。功率管理控制器可操作以将功率施加到其中一个时钟源并选择另一个时钟源以用于该电路的同步。然后，在稳定第一时钟源时，由电源管理控制器选择电路同步。

33. 发明申请

US20110085262A1 DLC-Head Offset Compensation While Writing 有权
标题翻译：写作时的DLC头偏移补偿
公开(公告)号：US20110085262A1
公开(公告)日：2011-04-14
申请号：US12861072
申请日：2010-08-23
申请人： Jeffrey Grundvig , Richard Rauschmayer
发明人： Jeffrey Grundvig , Richard Rauschmayer
IPC分类号： G11B5/596
CPC分类号： G11B5/012 , B82Y10/00 , G11B5/746 , G11B20/10009 , G11B20/10222 , G11B20/10398 , G11B20/14 , G11B2220/2516
摘要： In described embodiments, effects of frequency and phase error introduced at the outer diameter or inner diameter of the disk when a read head is used to maintain timing lock while the write head is used to write new data might be eliminated with a simple compensation circuit. Compensation circuits, modules or methods receive as input information i) write head radial position (e.g., from a wedge number that indicates the circumferential position of the heads), and ii) read head and write head relative physical offset. The timing error is measured by the system and might be automatically adjusted by the appropriate amount in order to reduce or to eliminate the differential head error when a write event (as opposed to a read event) is activated
摘要翻译：在所描述的实施例中，使用简单的补偿电路可以消除在写入头用于写入新数据时使用读取头来保持定时锁定时在盘的外径或内径处引入的频率和相位误差的影响。补偿电路，模块或方法作为输入信息接收i）写头径向位置（例如，从指示磁头的周向位置的楔形数），以及ii）读头和写头相对物理偏移。定时误差由系统测量，并且可以自动调整适当的量，以减少或消除当写入事件（与读取事件相反）被激活时的差分磁头错误

34. 发明授权

US07817363B2 Single-pass defect detection for hard-disk drive systems 有权
标题翻译：硬盘驱动器系统的单通道缺陷检测
公开(公告)号：US07817363B2
公开(公告)日：2010-10-19
申请号：US12272255
申请日：2008-11-17
申请人： Keenan T. O'Brien , Richard Rauschmayer
发明人： Keenan T. O'Brien , Richard Rauschmayer
IPC分类号： G11B27/36
CPC分类号： G11B20/1879 , G11B19/048 , G11B20/10037 , G11B20/10296 , G11B20/10314 , G11B20/1037 , G11B20/10379 , G11B20/10416 , G11B20/10425 , G11B20/1217 , G11B20/182 , G11B20/1833 , G11B2020/1277 , G11B2020/1281 , G11B2020/1287 , G11B2020/1289 , G11B2020/1823 , G11B2020/1826 , G11B2020/1836 , G11B2020/1863 , G11B2020/1896 , G11B2220/2516
摘要： In one embodiment, defects are detected on the face of a hard-disk drive platter. A preamble, a sync mark, user or pseudorandom data, and a data pad are written to every sector on a track of the platter. Inter-sector gaps that separate consecutive sectors are overwritten with a fixed data pattern such that consecutive sectors are in phase lock with one another. After the track has been written, the track is read back and analyzed. Consecutive sectors are analyzed continuously without stopping. The preambles, sync marks, data pads, and overwritten inter-sector gaps are analyzed using suitable flaw-scan techniques. The user or pseudorandom data is analyzed using both data-integrity checks and suitable flaw-scan techniques. This process is repeated for all tracks on the disk, and defect detection is completed when all tracks have been analyzed.
摘要翻译：在一个实施例中，在硬盘驱动器盘的表面上检测到缺陷。前导码，同步标记，用户或伪随机数据以及数据焊盘被写入盘的轨道上的每个扇区。使用固定数据模式覆盖分开连续扇区的扇区间间隙，使得连续的扇区彼此相位锁定。轨道写入后，回读和分析轨迹。不间断连续分析连续部门。使用合适的缺陷扫描技术分析前导码，同步标记，数据块和覆盖的扇区间间隙。使用数据完整性检查和合适的缺陷扫描技术分析用户或伪随机数据。对磁盘上的所有轨道重复此过程，并且在分析了所有轨道时完成缺陷检测。

35. 发明申请

US20100205462A1 Systems and Methods for Modular Power Management 有权
标题翻译：模块化电源管理的系统和方法
公开(公告)号：US20100205462A1
公开(公告)日：2010-08-12
申请号：US12280790
申请日：2006-07-18
申请人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
发明人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3268 , G06F1/3287 , G11B19/00 , Y02D10/128 , Y02D10/154 , Y02D10/171 , Y10T307/50
摘要： A modular, adaptive power management system includes a hard disk drive controller, a read channel module, a host interface controller and a power manager system. The hard disk controller includes a processor executing firmware, and the host interface controller provides for host access via a host interface. The system includes a power island register and an oscillation control register. Both registers are writable via the firmware and via the host interface. The hard disk controller, the interface controller, the read channel module and the power manager system are implemented across two or more distinct power islands and use two or more distinct clocks. Power to the two or more distinct power islands is at least in part controlled by the power manager system via the power island register, and the two or more distinct clocks are each controlled by the power manager system via the oscillation control register.
摘要翻译：模块化的自适应电源管理系统包括硬盘驱动器控制器，读通道模块，主机接口控制器和电源管理器系统。硬盘控制器包括执行固件的处理器，并且主机接口控制器通过主机接口提供主机访问。该系统包括功率岛寄存器和振荡控制寄存器。两个寄存器都可以通过固件和主机接口写入。硬盘控制器，接口控制器，读通道模块和电源管理器系统在两个或多个不同的电源岛之间实现，并且使用两个或更多个不同的时钟。两个或多个不同功率岛的功率至少部分地由功率管理器系统经由功率岛寄存器控制，并且两个或更多个不同时钟各自由功率管理器系统经由振荡控制寄存器来控制。

36. 发明申请

US20090161245A1 Frequency Domain Approach for Efficient Computation of Fixed-point Equalization Targets 有权
标题翻译：用于有效计算定点均衡目标的频域方法
公开(公告)号：US20090161245A1
公开(公告)日：2009-06-25
申请号：US12273265
申请日：2008-11-18
申请人： George Mathew , Yuan Xing Lee , Hongwei Song , Richard Rauschmayer
发明人： George Mathew , Yuan Xing Lee , Hongwei Song , Richard Rauschmayer
IPC分类号： G11B5/035
CPC分类号： G11B20/10212 , G11B20/10046 , G11B20/10194 , G11B20/24 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.
摘要翻译：本发明的各种实施例提供了用于均衡输入信号的系统和方法。例如，本发明的各种实施例提供了一种用于在存储设备中执行均衡的方法。这样的方法包括提供由目标值控制的均衡器电路和由滤波器系数控制的滤波器电路。将初始值作为目标值提供给均衡器电路，并且至少部分地基于初始值和滤波器系数来计算总体目标。基于总体目标计算更新的值，并且将更新的值作为目标值提供给均衡器电路。

37. 发明申请

US20080077818A1 Systems and Methods for Operational Power Management 失效
标题翻译：操作电源管理系统与方法
公开(公告)号：US20080077818A1
公开(公告)日：2008-03-27
申请号：US11534305
申请日：2006-09-22
申请人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
发明人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
IPC分类号： G06F1/12
CPC分类号： G06F1/3203 , G06F1/04 , G06F1/24 , G06F1/3268 , Y02D10/154
摘要： Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management controller. The power management controller is operable to apply power to one of the clock sources and to select another of the clock sources for synchronization of the circuit. Then, upon stabilization of the first clock source, it is selected by the power management controller to synchronize the circuit.
摘要翻译：本文公开了用于电力管理的各种系统和方法。例如，公开了包括两个或更多个时钟源和电源管理控制器的同步半导体电路。功率管理控制器可操作以将功率施加到其中一个时钟源并选择另一个时钟源以用于该电路的同步。然后，在稳定第一时钟源时，由电源管理控制器选择电路同步。

38. 发明申请

US20130073889A1 Systems and Methods for Modular Power Management 审中-公开
标题翻译：模块化电源管理的系统和方法
公开(公告)号：US20130073889A1
公开(公告)日：2013-03-21
申请号：US13646597
申请日：2012-10-05
申请人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
发明人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
IPC分类号： G06F1/26
CPC分类号： G06F1/3221 , G06F1/3237 , G06F1/3268 , G06F1/3287 , Y02D10/128 , Y02D10/154 , Y02D10/171
摘要： Various systems and methods for power management.
摘要翻译：各种电源管理系统和方法。

39. 发明授权

US08291251B2 Systems and methods for modular power management 有权
标题翻译：用于模块化电源管理的系统和方法
公开(公告)号：US08291251B2
公开(公告)日：2012-10-16
申请号：US12280790
申请日：2006-07-18
申请人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
发明人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3268 , G06F1/3287 , G11B19/00 , Y02D10/128 , Y02D10/154 , Y02D10/171 , Y10T307/50
摘要： Various systems and methods for power management are disclosed herein. For example, a modular, adaptive power management system for use in a hard disk drive system is disclosed. This modular, adaptive power management system includes a hard disk drive controller, a read channel module, a host interface controller and a power manager system. The hard disk controller includes a processor executing firmware, and the host interface controller provides for host access via a host interface. The host interface may be, for example, an ATA interface, a SATA interface, and/or other emerging serial interfaces such as MMC, CE-ATA or SDIO. The power manager system includes a power island register and an oscillation control register. Both the power island register and the oscillation control register are each at least indirectly writable via the firmware and via the host interface. The hard disk controller, the interface controller, the read channel module and the power manager system are implemented across two or more distinct power islands and use two or more distinct clocks. Power to the two or more distinct power islands is at least in part controlled by the power manager system via the power island register, and the two or more distinct clocks are each controlled by the power manager system via the oscillation control register.
摘要翻译：本文公开了用于电力管理的各种系统和方法。例如，公开了一种用于硬盘驱动器系统的模块化自适应电源管理系统。该模块化的自适应电源管理系统包括硬盘驱动器控制器，读通道模块，主机接口控制器和电源管理器系统。硬盘控制器包括执行固件的处理器，并且主机接口控制器通过主机接口提供主机访问。主机接口可以是例如ATA接口，SATA接口和/或其他新兴串行接口，例如MMC，CE-ATA或SDIO。功率管理器系统包括功率岛寄存器和振荡控制寄存器。功率岛寄存器和振荡控制寄存器都可以通过固件和主机接口至少间接写入。硬盘控制器，接口控制器，读通道模块和电源管理器系统在两个或多个不同的电源岛之间实现，并且使用两个或更多个不同的时钟。两个或多个不同功率岛的功率至少部分地由功率管理器系统经由功率岛寄存器控制，并且两个或更多个不同时钟各自由功率管理器系统经由振荡控制寄存器来控制。

40. 发明授权

US08233228B2 DLC-head offset compensation while writing 有权
标题翻译：写入时DLC头偏移补偿
公开(公告)号：US08233228B2
公开(公告)日：2012-07-31
申请号：US12861072
申请日：2010-08-23
申请人： Jeffrey Grundvig , Richard Rauschmayer
发明人： Jeffrey Grundvig , Richard Rauschmayer
IPC分类号： G11B5/09
CPC分类号： G11B5/012 , B82Y10/00 , G11B5/746 , G11B20/10009 , G11B20/10222 , G11B20/10398 , G11B20/14 , G11B2220/2516
摘要： In described embodiments, effects of frequency and phase error introduced at the outer diameter or inner diameter of the disk when a read head is used to maintain timing lock while the write head is used to write new data might be eliminated with a simple compensation circuit. Compensation circuits, modules or methods receive as input information i) write head radial position (e.g., from a wedge number that indicates the circumferential position of the heads), and ii) read head and write head relative physical offset. The timing error is measured by the system and might be automatically adjusted by the appropriate amount in order to reduce or to eliminate the differential head error when a write event (as opposed to a read event) is activated.
摘要翻译：在所描述的实施例中，使用简单的补偿电路可以消除在写入头用于写入新数据时使用读取头来保持定时锁定时在盘的外径或内径处引入的频率和相位误差的影响。补偿电路，模块或方法作为输入信息接收i）写头径向位置（例如，从指示磁头的圆周位置的楔形数），以及ii）读头和写头相对物理偏移。定时误差由系统测量，并且可以自动调整适当的量，以减少或消除写入事件（与读取事件相反）时的差动头错误。

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