专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08295073B2 Non-volatile dual port third dimensional memory 有权
标题翻译：非易失性双端口三维存储器
公开(公告)号：US08295073B2
公开(公告)日：2012-10-23
申请号：US12592319
申请日：2009-11-23
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C11/00
CPC分类号： G11C7/1075 , G11C8/14 , G11C8/16
摘要： Non-volatile dual port memory with third dimension memory is described, including a non-volatile third dimensional memory array comprising a memory element, the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage, a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, the transceiver gate is configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being coupled to the memory element and configured to provide the another voltage, and a plurality of word lines coupled to the memory element, the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports.
摘要翻译：描述了具有第三维存储器的非易失性双端口存储器，包括包括存储器元件的非易失性第三维存储器阵列，该存储器元件被配置为响应于电压从第一电阻状态改变到第二电阻状态，收发器门被配置为将电压栅极存储到存储器元件，该电压被配置为将存储元件从第一电阻状态改变到第二电阻状态，收发器门被配置为从位线和位条接收另一电压线，位线和位线连接到存储器元件并且被配置为提供另一电压，以及耦合到存储器元件的多个字线，多个字线被配置为提供基本上同时的访问使用两个或多个端口的非易失性第三维存储器阵列。

32. 发明授权

US08270196B2 Integrated circuits using non volatile resistivity sensitive memory for emulation of embedded flash memory 有权
标题翻译：使用非易失性电阻率敏感存储器的集成电路，用于仿真嵌入式闪存
公开(公告)号：US08270196B2
公开(公告)日：2012-09-18
申请号：US13303006
申请日：2011-11-22
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C5/06
CPC分类号： G06F13/4239 , G06F13/1694 , G11C7/10 , G11C7/22 , Y02D10/14 , Y02D10/151
摘要： Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another.
摘要翻译：公开了与至少一个非易失性电阻率敏感存储器通信的接口电路。存储器包括可以具有两个端子的多个非易失性存储器元件，其可操作以将数据存储为可以通过在存储器元件上施加读取电压来确定的多个导电率曲线，并且在不存在时保留存储的数据的权力。可以以交叉点阵列配置布置多个存储器元件。接口电路与例如DRAM，SRAM和FLASH等存储器类型的系统进行电气通信，并且可操作地与非易失性电阻率敏感存储器通信以模拟这些存储器类型中的一个或多个。接口电路可以在衬底上的逻辑平面中制造，其中至少一个非易失性电阻率敏感存储器垂直定位在逻辑平面上。非易失性电阻率敏感存储器可以彼此垂直堆叠。

33. 发明授权

US08259520B2 Columnar replacement of defective memory cells 有权
标题翻译：柱状更换有缺陷的记忆细胞
公开(公告)号：US08259520B2
公开(公告)日：2012-09-04
申请号：US12592330
申请日：2009-11-23
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/00
CPC分类号： G11C5/02 , G11C29/808
摘要： Circuits and methods to compensate for defective memory in BEOL third dimensional memory technology are described. An integrated circuit is configured to perform columnar replacement of defective BEOL multi-layered memory. For example, the integrated circuit can include a primary BEOL memory array having a plurality of BEOL memory cells being configured to change resistivity, a secondary BEOL memory array having another plurality of BEOL memory cells being configured to change resistivity, and a FEOL restoration module associated with the primary BEOL memory array and the secondary BEOL memory array, the FEOL restoration module being configured to locate a BEOL memory cell within the secondary BEOL memory array to replace a defective BEOL memory cell within the primary BEOL memory array. The FEOL portion can be fabricated on a substrate and the BEOL portion can be fabricated above and in contact with the FEOL portion to form the integrated circuit.
摘要翻译：描述了用于补偿BEOL第三维存储器技术中的缺陷存储器的电路和方法。集成电路被配置为执行有缺陷的BEOL多层存储器的柱状替换。例如，集成电路可以包括主BEOL存储器阵列，其具有被配置为改变电阻率的多个BEOL存储器单元，具有另外多个BEOL存储器单元的次级BEOL存储器阵列被配置为改变电阻率，以及FEOL恢复模块相关联与主要BEOL存储器阵列和次级BEOL存储器阵列一起，FEOL恢复模块被配置为定位次级BEOL存储器阵列内的BEOL存储器单元以替代主BEOL存储器阵列内的有缺陷的BEOL存储器单元。 FEOL部分可以制造在基板上，并且BEOL部分可以制造在FEOL部分的上方并与其接触以形成集成电路。

34. 发明授权

US08165621B2 Memory emulation in a cellular telephone 有权
标题翻译：蜂窝电话中的内存仿真
公开(公告)号：US08165621B2
公开(公告)日：2012-04-24
申请号：US11974034
申请日：2007-10-10
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H04M1/00 , H04M3/42 , G06F13/00 , G06F13/14 , G06F13/36 , G11C5/02 , G11C5/06 , G11C19/08
CPC分类号： G06F12/0238 , G06F9/455 , G06F12/0638 , G06F2212/2024 , Y02D10/13
摘要： A cellular telephone using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the cellular telephone. At least one of the memory arrays may be in the form of a removable memory card.
摘要翻译：公开了一种使用直接寻址和非易失性存储器阵列的蜂窝电话。存储器阵列可以用于替换和仿真多种存储器类型，例如DRAM，SRAM，非易失性RAM，FLASH存储器和非易失性存储卡。可以随机访问存储器阵列。存储在存储器阵列中的数据在没有电力的情况下被保留。在蜂窝电话中可以使用一个或多个存储器阵列。存储器阵列中的至少一个可以是可移动存储卡的形式。

35. 发明授权

US08164937B2 Digital potentiometer using third dimensional memory 失效
标题翻译：数字电位器采用三维存储器
公开(公告)号：US08164937B2
公开(公告)日：2012-04-24
申请号：US12653897
申请日：2009-12-18
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C5/06
CPC分类号： H03G1/0088 , H03G3/001 , H03H11/24
摘要： A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such as a third dimensional memory element. The non-volatile register can include a FEOL active circuitry portion that is electrically coupled with the BEOL non-volatile memory element to implement the non-volatile register. The resistive elements can be BEOL resistive elements that can be fabricated on the same plane or a different plane than the BEOL non-volatile memory elements. The BEOL non-volatile memory elements and the BEOL resistive elements can retain stored data in the absence of power and the stored data can be non-destructively determined by application of a read voltage.
摘要翻译：使用第三维存储器的数字电位器包括被配置为将一个或多个电阻元件与第一引脚和第二引脚电耦合的开关以及被配置为控制开关的非易失性寄存器。在一个示例中，非易失性寄存器可以包括诸如第三维存储器元件的BEOL非易失性存储器元件。非易失性寄存器可以包括与BEOL非易失性存储器元件电耦合以实现非易失性寄存器的FEOL有源电路部分。电阻元件可以是可以制造在与BEOL非易失性存储器元件相同的平面或不同平面上的BEOL电阻元件。 BEOL非易失性存储器元件和BEOL电阻元件可以在没有电力的情况下保留存储的数据，并且存储的数据可以通过应用读取电压而非破坏性地确定。

36. 发明授权

US08032692B2 System for accessing non-volatile memory 失效
标题翻译：用于访问非易失性存储器的系统
公开(公告)号：US08032692B2
公开(公告)日：2011-10-04
申请号：US12931198
申请日：2011-01-25
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G11C5/02 , G11C13/0002 , G11C2213/71 , Y02D10/13
摘要： Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data.
摘要翻译：描述访问非易失性存储器阵列，包括接收与第一数据相关联的第一数据和存储器地址，将第一数据写入第一数据的存储器地址处的非易失性存储器阵列，而不擦除存储的第二数据在非易失性存储器阵列中的第一个数据的存储器地址写入第一个数据之前。

37. 发明授权

US08004309B2 Programmable logic device structure using third dimensional memory 有权
标题翻译：使用第三维存储器的可编程逻辑器件结构
公开(公告)号：US08004309B2
公开(公告)日：2011-08-23
申请号：US12657684
申请日：2010-01-25
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17748 , H03K19/1778 , H03K19/17796
摘要： A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.
摘要翻译：公开了一种使用第三维存储器的可编程逻辑器件（PLD）结构。 PLD结构包括被配置为将信号的极性（例如，施加到输入的输入信号）耦合到路由线路的开关和被配置为控制开关的非易失性寄存器。非易失性寄存器可以包括诸如第三维存储元件的非易失性存储元件。非易失性存储器元件可以是在没有电力的情况下保存存储的数据并将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地感测的多个电导率分布的两端存储元件。可以通过在两个端子上施加写入电压将新数据写入到两端存储元件。逻辑和其它有源电路可以被定位在衬底中，并且非易失性存储元件可以被定位在衬底的顶部上。

38. 发明申请

US20110188291A1 Preservation circuit and methods to maintain values representing data in one or more layers of memory 失效
标题翻译：保存电路和保持在一层或多层存储器中表示数据的值的方法
公开(公告)号：US20110188291A1
公开(公告)日：2011-08-04
申请号：US12932637
申请日：2011-03-01
申请人： Christophe Chevallier , Robert Norman
发明人： Christophe Chevallier , Robert Norman
IPC分类号： G11C11/00
CPC分类号： G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
摘要翻译：公开了用于恢复存储器中的数据的电路和方法。存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

39. 发明申请

US20110173408A1 Securing non-volatile data in an embedded memory device 失效
公开(公告)号：US20110173408A1
公开(公告)日：2011-07-14
申请号：US13065504
申请日：2011-03-22
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F12/14
CPC分类号： G11C7/24 , G11C5/02
摘要： The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory.

40. 发明申请

US20110141831A1 READ BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS 有权
标题翻译：用于在集成电路中访问多个存储器层的读缓冲系统
公开(公告)号：US20110141831A1
公开(公告)日：2011-06-16
申请号：US12931966
申请日：2011-02-15
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/00
CPC分类号： G11C7/1096 , G11C5/02 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C8/10 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C2013/0085 , G11C2013/0088 , G11C2213/71 , G11C2216/14
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.
摘要翻译：本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。例如，集成电路可以包括设置在多层存储器中的存储单元。在一个实施例中，存储器单元可以是第三维存储器单元。集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式