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31. 再颁专利

USRE45604E1 DLL circuit adapted to semiconductor device 有权
标题翻译： DLL电路适用于半导体器件
公开(公告)号：USRE45604E1
公开(公告)日：2015-07-07
申请号：US14020445
申请日：2013-09-06
申请人： PS4 Luxco S.a.r.l.
发明人： Koji Kuroki , Ryuuji Takishita
IPC分类号： H03L7/06 , H03L7/081
CPC分类号： H03L7/0814
摘要： A DLL circuit is designed to adjust the delay time and the duty applied to an input clock signal, thus producing a DLL clock signal. In a non-clocking state of the DLL clock signal in which pulses disappear temporarily, the DLL circuit stops updating the delay time and the duty of the DLL clock signal. That is, the DLL circuit is capable of preventing a phase difference between the input clock signal and the DLL clock signal from being erroneously detected in the non-clocking state of the DLL clock signal, thus preventing the delay time and the duty from being updated based on the erroneously detected phase difference. Thus, it is possible to reduce the number of cycles adapted to the delay-locked control and to thereby stabilize the operation of the DLL circuit.
摘要翻译： DLL电路被设计为调整延迟时间和施加到输入时钟信号的占空比，从而产生DLL时钟信号。在其中脉冲消失的DLL时钟信号的非时钟状态下，DLL电路停止更新延迟时间和DLL时钟信号的占空比。也就是说，DLL电路能够防止在DLL时钟信号的非时钟状态下错误地检测输入时钟信号和DLL时钟信号之间的相位差，从而防止延迟时间和占空比被更新基于错误检测的相位差。因此，可以减少适应于延迟锁定控制的周期数，从而稳定DLL电路的操作。

32. 发明授权

US09076500B2 Memory module including plural memory devices and data register buffer 有权
标题翻译：存储器模块包括多个存储器件和数据寄存器缓冲器
公开(公告)号：US09076500B2
公开(公告)日：2015-07-07
申请号：US13685192
申请日：2012-11-26
申请人： Elpida Memory, Inc.
发明人： Fumiyuki Osanai , Toshio Sugano , Atsushi Hiraishi
IPC分类号： G11C5/04 , G11C7/10 , G11C11/4093
CPC分类号： G11C5/04 , G11C7/1057 , G11C7/1084 , G11C11/4093
摘要： Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.
摘要翻译：这里公开了一种存储器模块，其包括模块衬底，数据连接器，存储器件和数据寄存器缓冲器。模块基板的第一主表面具有第一和第二存储器安装区域。模块基板的第一和第二主表面之一具有在计划视图中位于第一和第二存储器安装区域之间的寄存器安装区域。存储器件包括安装在第一存储器安装区域上的多个第一存储器件和安装在第二存储器安装区域上的多个第二存储器件。数据寄存器缓冲器安装在寄存器安装区域。数据寄存器缓冲器将从数据连接器提供的写入数据传送到存储器件，并将从存储器件提供的读取数据传送到数据连接器。

33. 发明授权

US09053821B2 Semiconductor device performing stress test 有权
标题翻译：半导体器件进行压力测试
公开(公告)号：US09053821B2
公开(公告)日：2015-06-09
申请号：US14243183
申请日：2014-04-02
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshiro Riho , Hiromasa Noda , Kazuki Sakuma
IPC分类号： G11C7/00 , G11C29/00 , G11C29/06 , G11C29/12 , G11C29/28 , G11C29/02 , G11C29/50 , G11C29/26
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.
摘要翻译：半导体器件包括存储单元阵列，其通过多个读出放大器阵列被分成多个存储单元阵列，并且多个存储单元阵列中的每一个包括多个字线和用于执行测试控制的测试电路一次激活在多个存储单元垫中彼此不邻近设置的多个所选存储单元垫中的每一个中包括的多个字线。根据本发明，分配具有多个激活字线的存储单元垫。因此，与在一个存储单元垫中激活的许多字线相比，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小。因此，可以同时激活更多的字线。

34. 发明授权

US09053759B2 Semiconductor device having plural selection lines 有权
标题翻译：具有多个选择线的半导体装置
公开(公告)号：US09053759B2
公开(公告)日：2015-06-09
申请号：US13683538
申请日：2012-11-21
申请人： PS4 Luxco S.a.r.l.
发明人： Hidekazu Noguchi
IPC分类号： G11C8/06 , G11C7/00 , G11C8/08 , G11C8/14 , G11C11/408 , G11C11/4097
CPC分类号： G11C11/4094 , G11C7/00 , G11C8/06 , G11C8/08 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097
摘要： The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group.
摘要翻译：半导体器件包括分为多个组的多个字线和用于根据地址选择字线的选择电路。选择电路具有为每个组布置的电平移位器。地址包括用于选择任何组的第一地址和用于选择所选组中的字线的第二地址。选择电路通过由由第一地址选择的组的电平移位器提供字线的有效电位来选择字线，并且还允许向由多个第一地址中的第二地址选择的字线提供有效电位属于所选组的字线。

35. 发明授权

US09047986B2 Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit 有权
公开(公告)号：US09047986B2
公开(公告)日：2015-06-02
申请号：US13468691
申请日：2012-05-10
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： G11C29/02 , H03K17/16 , H03K19/003 , G01R31/317 , G11C29/50
CPC分类号： H03H11/28 , G01R31/31713 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , H03K19/0005
摘要： To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

36. 发明授权

US09041436B2 Semiconductor device having pull-up circuit and pull-down circuit 有权
标题翻译：具有上拉电路和下拉电路的半导体器件
公开(公告)号：US09041436B2
公开(公告)日：2015-05-26
申请号：US13317696
申请日：2011-10-26
申请人： Shunji Kuwahara , Hiroki Fujisawa
发明人： Shunji Kuwahara , Hiroki Fujisawa
IPC分类号： H03K3/00 , G11C11/4074 , G11C5/06 , G11C7/10 , G11C11/4093
CPC分类号： G11C11/4074 , G11C5/063 , G11C7/1057 , G11C11/4093 , Y10T307/50
摘要： To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.
摘要翻译：为了减少用于控制输出缓冲器的控制电路单元中发生的电源噪声。半导体器件包括用于驱动数据输出端子的单元缓冲器，用于控制单元缓冲器的阻抗控制电路，以及用于控制阻抗控制电路的控制电路单元。阻抗控制电路和控制电路单元通过相互不同的电源进行工作，控制电路单元向阻抗控制电路提供相互反相的上拉数据和下拉数据，并且阻抗控制电路将拉 - 并将下拉数据从反相到同相，并将其提供给单元缓冲器。因此，在用于控制电路单元的电源VDD中难以发生噪声。

37. 发明授权

US09036448B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09036448B2
公开(公告)日：2015-05-19
申请号：US13415777
申请日：2012-03-08
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C8/18 , H03K21/40
CPC分类号： G11C8/18 , H03K21/406
摘要： A device includes a first clock generation circuit that receives an external clock signal supplied to the device, delays the external clock signal to output a first clock signal synchronized with the external clock signal, and a circuit that generates a control signal to control output of data, based on second clock signals obtained by dividing an internal clock signal generated from the external clock signal, and third clock signals obtained by dividing the first clock signal.
摘要翻译：一种设备包括：第一时钟产生电路，其接收提供给该设备的外部时钟信号，延迟外部时钟信号以输出与外部时钟信号同步的第一时钟信号，以及产生控制信号以控制数据输出的电路基于通过对从外部时钟信号产生的内部时钟信号进行分频而获得的第二时钟信号和通过划分第一时钟信号而获得的第三时钟信号。

38. 发明授权

US09024428B2 Semiconductor device and stacked semiconductor device 有权
标题翻译：半导体器件和堆叠半导体器件
公开(公告)号：US09024428B2
公开(公告)日：2015-05-05
申请号：US14306638
申请日：2014-06-17
申请人： PS4 Luxco S.a.r.l.
发明人： Masahiro Yamaguchi , Hiroaki Ikeda
IPC分类号： H01L23/02 , H01L23/00 , H01L21/66 , H01L23/48 , H01L23/498 , H01L25/065 , H01L23/31 , H01L23/36
CPC分类号： H01L24/02 , H01L22/30 , H01L22/32 , H01L23/3128 , H01L23/3135 , H01L23/36 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05572 , H01L2224/05624 , H01L2224/05666 , H01L2224/13009 , H01L2224/13021 , H01L2224/13082 , H01L2224/13147 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06565 , H01L2225/06596 , H01L2924/00014 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/15311 , H01L2224/05552
摘要： A semiconductor device includes a package substrate, and a stack of semiconductor chips over the package substrate, each of the semiconductor chips including first and second surfaces, each of the semiconductor chips including a first through electrode that extends through each of the semiconductor chips, a first surface electrode positioned on the first surface of each of the semiconductor chips, the first surface electrode being coupled to a first end of the first through electrode, a second surface electrode positioned on the second surface of each of the semiconductor chips, the second surface electrode being coupled to a second end of the first through electrode, a second through electrode that extends through each of the semiconductor chips, the second through electrode having third and fourth ends, and a third surface electrode positioned on the second surface of the first semiconductor chip.
摘要翻译：半导体器件包括封装衬底和在封装衬底上的堆叠的半导体芯片，每个半导体芯片包括第一和第二表面，每个半导体芯片包括延伸穿过每个半导体芯片的第一贯通电极，第一表面电极位于每个半导体芯片的第一表面上，第一表面电极耦合到第一通孔的第一端，位于每个半导体芯片的第二表面上的第二表面电极，第二表面电极电极耦合到第一通孔的第二端，延伸穿过每个半导体芯片的第二贯通电极，具有第三和第四端的第二贯通电极和位于第一半导体的第二表面上的第三表面电极芯片。

39. 发明授权

US09019787B2 Semiconductor device having hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体器件
公开(公告)号：US09019787B2
公开(公告)日：2015-04-28
申请号：US13888707
申请日：2013-05-07
申请人： PS4 Luxco S.A.R.L.
发明人： Yasuhiro Matsumoto , Noriaki Mochida , Takeshi Ohgami , Daiki Izawa
IPC分类号： G11C7/00 , G11C5/06 , G11C11/4074 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C7/18 , G11C29/00 , G11C29/06 , G11C29/12
CPC分类号： G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C29/006 , G11C29/06 , G11C2029/1204
摘要： A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.
摘要翻译：公开了一种具有分层位线的半导体器件，其包括：第一全局位线; 第一和第二局部位线共同耦合到第一全局位线; 第一和第二电力线; 耦合在第一局部位线和第一电源线之间的第一晶体管; 耦合在所述第二局部位线和所述第二电源线之间的第二晶体管; 耦合在第一和第二电力线之间的第三晶体管。

40. 发明授权

US09001610B2 Semiconductor device generating internal voltage 有权
标题翻译：产生内部电压的半导体器件
公开(公告)号：US09001610B2
公开(公告)日：2015-04-07
申请号：US13316293
申请日：2011-12-09
申请人： Takuyo Kodama
发明人： Takuyo Kodama
IPC分类号： G11C5/14 , G11C11/24 , H03K19/00
CPC分类号： H03K19/0016 , G11C5/145 , G11C5/147
摘要： Such a device is disclosed that includes an internal voltage generating circuit generating an internal voltage by lowering an external potential and supplying the generated internal voltage to a power supply line, a switch being connected between a grounding wire to which a ground voltage is supplied and the power supply line, and a one-shot signal generating unit controlling turning on and off of the switch, wherein the one-shot signal generating unit brings the switch into conduction synchronously with start of generating the internal voltage by the internal voltage generating circuit.
摘要翻译：公开了这样一种装置，其包括通过降低外部电位产生内部电压并将产生的内部电压提供给电源线的内部电压产生电路，开关连接在提供接地电压的接地线和电源线，以及控制开关的接通和断开的单触发信号发生单元，其中单触发信号发生单元使内部电压产生电路产生内部电压的开始同步地使开关导通。

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