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31. 发明授权

US08693163B2 Cylindrical embedded capacitors 有权
标题翻译：圆柱形嵌入式电容器
公开(公告)号：US08693163B2
公开(公告)日：2014-04-08
申请号：US12873931
申请日：2010-09-01
申请人： An-Jhih Su , Chi-Chun Hsieh , Tzu-Yu Wang , Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
发明人： An-Jhih Su , Chi-Chun Hsieh , Tzu-Yu Wang , Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
IPC分类号： H01L29/92 , H01L21/768
CPC分类号： H01L28/40 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/14 , H01L28/92 , H01L2224/0401 , H01L2224/05008 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14181 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.
摘要翻译：一种装置包括具有与前表面相对的前表面和后表面的基底。电容器形成在衬底中，并包括第一电容器板; 围绕所述第一电容器板的第一绝缘层; 以及环绕所述第一绝缘层的第二电容器板。第一电容器板，第一绝缘层和第二电容器板中的每一个从基板的前表面延伸到后表面。

32. 发明授权

US08669605B2 Semiconductor device and arrangement method of compensation capacitor of semiconductor device 失效
标题翻译：半导体器件补偿电容器的半导体器件和布置方法
公开(公告)号：US08669605B2
公开(公告)日：2014-03-11
申请号：US12722101
申请日：2010-03-11
申请人： Yoshiaki Shimizu
发明人： Yoshiaki Shimizu
IPC分类号： H01L29/92 , H01L29/93
CPC分类号： H01L29/94 , H01L27/0207 , H01L27/0629 , H01L27/11807
摘要： A semiconductor device comprises a circuit cell and a basic end cell. The circuit cell includes a plurality of elements aligned in a first direction, and the basic end cell is arranged adjacent to the circuit cell in the first direction and has a compensation capacitor capable of being connected to a supply voltage of the circuit cell. In the semiconductor device, a diffusion layer forming the compensation capacitor extends along the first direction in a predetermined region of the circuit cell.
摘要翻译：半导体器件包括电路单元和基本端单元。电路单元包括沿第一方向排列的多个元件，并且基本端单元沿着第一方向布置成与电路单元相邻，并且具有能够连接到电路单元的电源电压的补偿电容器。在半导体器件中，形成补偿电容器的扩散层沿电路单元的预定区域中的第一方向延伸。

33. 发明申请

US20140042590A1 Metal-Insulator-Metal Capacitor and Method of Fabricating 有权
标题翻译：金属绝缘体 - 金属电容器和制造方法
公开(公告)号：US20140042590A1
公开(公告)日：2014-02-13
申请号：US13571441
申请日：2012-08-10
申请人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
发明人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
IPC分类号： H01L29/92
CPC分类号： H01L28/60 , H01L28/75 , H01L29/92
摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
摘要翻译：公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。

34. 发明授权

US08614497B2 Method for fabricating a MIM capacitor using gate metal for electrode and related structure 有权
标题翻译：用于电极栅极金属和相关结构的MIM电容器的制造方法
公开(公告)号：US08614497B2
公开(公告)日：2013-12-24
申请号：US12462692
申请日：2009-08-07
申请人： Wei Xia , Xiangdong Chen , Akira Ito
发明人： Wei Xia , Xiangdong Chen , Akira Ito
IPC分类号： H01L29/92
CPC分类号： H01L27/0629 , H01L28/60
摘要： According to one exemplary embodiment, a method for fabricating a MIM capacitor in a semiconductor die includes forming a dielectric one segment over a substrate and a metal one segment over the dielectric one segment, where the metal one segment forms a lower electrode of the MIM capacitor. The method further includes forming a dielectric two segment over the dielectric one segment and a metal two segment over the dielectric two segment, where a portion of the metal two segment forms an upper electrode of the MIM capacitor. The metal one segment comprises a first gate metal. The metal two segment can comprise a second gate metal.
摘要翻译：根据一个示例性实施例，一种用于在半导体管芯中制造MIM电容器的方法包括在电介质一段上形成电介质一段并在电介质一段上形成金属一段，其中金属一段形成MIM电容器的下电极。该方法还包括在电介质一段上形成电介质两段，在电介质两段上形成金属二段，其中金属二段的一部分形成MIM电容器的上电极。金属一段包括第一栅极金属。金属二段可以包括第二栅极金属。

35. 发明申请

US20130328167A1 SELF-ALIGNED METAL-INSULATOR-METAL (MIM) CAPACITOR 审中-公开
标题翻译：自对准金属绝缘子 - 金属（MIM）电容器
公开(公告)号：US20130328167A1
公开(公告)日：2013-12-12
申请号：US13489940
申请日：2012-06-06
申请人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/75 , H01L23/5223 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the lower electrode, and an upper electrode, i.e., a second conductive material, positioned between vertical portions of the dielectric material liner and atop a horizontal connecting portion of the dielectric material liner. In accordance with the present disclosure, the vertical portions of the dielectric material liner do not extend onto an upper surface of the dielectric material that includes the lower electrode.
摘要翻译：提供集成在后端（BEOL）结构中的金属 - 绝缘体 - 金属（MIM）电容器结构。 MIM电容器结构包括嵌入在BEOL结构的电介质材料中的下电极，即第一导电材料，具有等于或大于位于下电极顶部的二氧化硅的介电常数的介电材料衬垫，以及位于电介质材料衬垫的垂直部分之间并且位于介电材料衬里的水平连接部分顶部的上电极，即第二导电材料。根据本公开，电介质材料衬垫的垂直部分不延伸到包括下电极的电介质材料的上表面上。

36. 发明申请

US20130320495A1 Integration of Non-Noble DRAM Electrode 有权
标题翻译：非贵重DRAM电极的集成
公开(公告)号：US20130320495A1
公开(公告)日：2013-12-05
申请号：US13738510
申请日：2013-01-10
申请人： INTERMOLECULAR, INC.
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Edward L. Haywood , Hiroyuki Ode , Gerald Richardson
IPC分类号： H01L29/92
CPC分类号： H01L29/92 , H01L28/75 , H01L28/92
摘要： A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.
摘要翻译：描述形成电容器堆叠的方法。在本发明的一些实施例中，第一电极结构由多种材料构成。在基板上方形成第一材料。蚀刻第一材料的一部分。在第一材料上方形成第二材料。蚀刻第二材料的一部分。可选地，第一电极结构接受退火处理。介电材料形成在第一电极结构之上。可选地，电介质材料接受退火处理。在电介质材料上方形成第二电极材料。通常，电容器堆叠接收退火处理。

37. 发明申请

US20130234291A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130234291A1
公开(公告)日：2013-09-12
申请号：US13733723
申请日：2013-01-03
申请人： Noboru MIYAMOTO , Yoshikazu TSUNODA
发明人： Noboru MIYAMOTO , Yoshikazu TSUNODA
IPC分类号： H01L29/92
CPC分类号： H01L29/92 , H01G4/232 , H01G4/30 , H01G4/33 , H01G4/40 , H01L23/49562 , H01L23/49589 , H01L23/642 , H01L24/32 , H01L25/16 , H01L28/82 , H01L28/86 , H01L28/90 , H01L2924/13055 , H01L2924/00
摘要： A semiconductor device includes a first electrode electrically connected to an upper surface of a semiconductor element, a first internal electrode electrically connected to a lower surface of the semiconductor element and having a plurality of first comb finger portions and a first connection portion connecting the plurality of first comb finger portions together, a second electrode electrically connected to the first internal electrode, a second internal electrode electrically connected to a lower surface of the first electrode and having a plurality of second comb finger portions and a second connection portion connecting the plurality of second comb finger portions together, the plurality of second comb finger portions being interdigitated with but not in contact with the plurality of first comb finger portions, and a lower dielectric filling the space between the plurality of first comb finger portions and the plurality of second comb finger portions.
摘要翻译：半导体器件包括电连接到半导体元件的上表面的第一电极，与半导体元件的下表面电连接并具有多个第一梳状指部的第一内部电极和连接多个电连接到第一内部电极的第二电极，与第一电极的下表面电连接并具有多个第二梳形指状部分的第二内部电极和连接多个第二梳状部分的第二连接部分，梳状指部分在一起，多个第二梳状指部分与多个第一梳状指部分相互交错但不接触;以及下部电介质，其填充多个第一梳状指部分与多个第二梳状指状部分之间的空间部分。

38. 发明申请

US20130221483A1 Trench Capacitors and Methods of Forming the Same 有权
公开(公告)号：US20130221483A1
公开(公告)日：2013-08-29
申请号：US13405092
申请日：2012-02-24
申请人： Thomas Popp , Stefan Pompl , Rudolf Berger
发明人： Thomas Popp , Stefan Pompl , Rudolf Berger
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/90 , H01L27/0805
摘要： A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.

39. 发明申请

US20130200482A1 SHALLOW TRENCH ISOLATION FOR DEVICE INCLUDING DEEP TRENCH CAPACITORS 失效
标题翻译：用于包括深层电容电容器的器件的低温隔离
公开(公告)号：US20130200482A1
公开(公告)日：2013-08-08
申请号：US13366576
申请日：2012-02-06
申请人： Sunfei FANG , Oleg GLUSCHENKOV , Byeong Y. KIM , Rishikesh KRISHNAN , Daewon YANG
发明人： Sunfei FANG , Oleg GLUSCHENKOV , Byeong Y. KIM , Rishikesh KRISHNAN , Daewon YANG
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/10861 , H01L21/76224 , H01L29/66181 , H01L29/945
摘要： A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.
摘要翻译：在包括沟槽电容元件的器件的有源区中形成浅沟槽隔离（STI）的方法，包括金属板和高k电介质的沟槽电容元件包括在器件的有源区中蚀刻STI沟槽，其中所述STI沟槽直接邻近所述沟槽电容元件的金属板或高k电介质中的至少一个; 以及在所述STI沟槽中形成氧化物衬垫，其中所述氧化物衬垫选择性地形成到所述金属板或高k电介质，其中形成所述氧化物衬垫在约600℃或更低的温度下进行。

40. 发明授权

US08502341B2 Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device 有权
标题翻译：沟槽型电容器，具有该沟槽型电容器的半导体器件和具有半导体器件的半导体模块
公开(公告)号：US08502341B2
公开(公告)日：2013-08-06
申请号：US13021333
申请日：2011-02-04
申请人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
发明人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
IPC分类号： H01L29/92
CPC分类号： H01L29/92
摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
摘要翻译：提供了沟槽型电容器。为了形成电容器，第一和第二有源区域设置在半导体衬底中。节点图案设置在第一活动区域中。每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。杂质扩散区域设置在节点图案附近。设置与第一和第二有源区电接触的衬底连接图案。与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

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