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41. 发明授权

US08981329B1 Method of forming anneal-resistant embedded resistor for non-volatile memory application 有权
标题翻译：用于非易失性存储器应用的形成耐退火嵌入式电阻器的方法
公开(公告)号：US08981329B1
公开(公告)日：2015-03-17
申请号：US14548408
申请日：2014-11-20
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Mihir Tendulkar , David Chi
IPC分类号： H01L29/02 , H01L45/00 , H01L49/02 , H01L27/24
CPC分类号： H01L45/146 , H01L21/28506 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L28/24 , H01L45/06 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/1616 , H01L45/1641
摘要： Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.
摘要翻译：本发明的实施例包括具有改进的器件性能和寿命的非易失性电阻随机存取存储器件的非易失性存储器件。在一些实施例中，非易失性电阻随机存取存储器件包括二极管，金属氮化硅嵌入式电阻器和设置在第一电极层和第二电极层之间的电阻开关层。在一些实施例中，形成电阻随机存取存储器件的方法包括形成二极管，形成金属氮化硅嵌入式电阻器，形成第一电极层，形成第二电极层，以及形成电阻开关层，层和第二电极层。

42. 发明申请

US20150070965A1 FET LOW CURRENT 3D ReRAM NON-VOLATILE STORAGE 审中-公开
标题翻译： FET低电流3D ReRAM非易失性存储
公开(公告)号：US20150070965A1
公开(公告)日：2015-03-12
申请号：US14025420
申请日：2013-09-12
申请人： SanDisk 3D LLC
发明人： Abhijit Bandyopadhyay , Roy E. Scheuerlein , Chandrasekhar R. Gorla , Brian Le
IPC分类号： G11C13/00
CPC分类号： G11C13/0059 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/148
摘要： Non-volatile storage devices having reversible resistance storage elements are disclosed herein. In one aspect, a memory cell unit includes one or more memory cells and a transistor (e.g., FET) that is used to control (e.g., limit) current of the memory cells. The drain of the transistor may be connected to a first end of the memory cell. If the memory cell unit has multiple memory cells then the drain may be connected to a node that is common to a first end of each of the memory cells. The source of the transistor is connected to a common source line. The gate of the transistor may be connected to a word line. The same word line may connect to the transistor gate of several (or many) different memory cell units. A second end of the memory cell is connected to a bit line.
摘要翻译：本文公开了具有可逆电阻存储元件的非易失性存储装置。在一个方面，存储单元单元包括一个或多个存储器单元和用于控制（例如，限制）存储器单元的电流的晶体管（例如，FET）。晶体管的漏极可以连接到存储单元的第一端。如果存储单元单元具有多个存储器单元，则漏极可以连接到每个存储器单元的第一端公用的节点。晶体管的源极连接到公共源极线。晶体管的栅极可以连接到字线。相同的字线可以连接到几个（或许多）不同存储单元单元的晶体管栅极。存储单元的第二端连接到位线。

43. 发明授权

US08969845B2 Memory cells having storage elements that share material layers with steering elements and methods of forming the same 有权
标题翻译：具有与转向元件共享材料层的存储元件的存储单元及其形成方法
公开(公告)号：US08969845B2
公开(公告)日：2015-03-03
申请号：US14299240
申请日：2014-06-09
申请人： SanDisk 3D LLC
发明人： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxwell , Kun Hou
IPC分类号： H01L47/00 , H01L29/02 , H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1616 , Y10S438/957
摘要： A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided.
摘要翻译：提供了一种存储单元，其包括转向元件，与转向元件串联耦合的金属 - 绝缘体 - 金属叠层以及金属 - 绝缘体 - 金属叠层上方的导体。该转向元件包括具有n区和p区的二极管。金属 - 绝缘体 - 金属堆叠包括在顶部电极和底部电极之间的可逆电阻率切换材料，并且顶部电极包括高度掺杂的半导体材料。存储单元不包括设置在金属 - 绝缘体 - 金属叠层和导体之间的金属层。底部电极包括二极管的n区域或p区域，并且可逆电阻率切换材料直接邻近二极管的n区域或p区域。提供了许多其他方面。

44. 发明授权

US08951861B2 Methods of making a high-density nonvolatile memory 有权
标题翻译：制造高密度非易失性存储器的方法
公开(公告)号：US08951861B2
公开(公告)日：2015-02-10
申请号：US13776193
申请日：2013-02-25
申请人： SanDisk 3D LLC
发明人： Scott Brad Herner , Maitreyee Mahajani
IPC分类号： H01L21/336
CPC分类号： G11C5/02 , H01L21/8238 , H01L23/48 , H01L27/1021 , H01L27/148 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.
摘要翻译：提供了用于形成单片三维存储器阵列的方法。一种示例性方法包括：（a）在衬底上方形成第一多个基本平行的基本共面的导体; （b）在所述第一多个基本平行的基本上共面的导体上形成第一多个半导体元件; 以及（c）在所述第一多个半导体元件上方形成第二多个基本平行的基本共面的导体。第一多个半导体元件中的每一个包括具有第一导电类型的第一重掺杂层，在第一重掺杂层上并与第一重掺杂层接触的第二轻掺杂层，以及与第二重掺杂层接触的第三重掺杂层掺杂层。第三重掺杂层具有与第一导电类型相反的第二导电类型。提供了许多其他方面。

45. 发明申请

US20150017780A1 Nonvolatile Resistive Memory Element With an Integrated Oxygen Isolation Structure 审中-公开
标题翻译：具有集成氧隔离结构的非易失性电阻式存储元件
公开(公告)号：US20150017780A1
公开(公告)日：2015-01-15
申请号：US14504620
申请日：2014-10-02
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Dipankar Pramanik
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/2463 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.
摘要翻译：非易失性电阻存储元件包括一个或多个新颖的氧隔离结构，其保护存储元件的电阻开关材料免于氧迁移。一个这样的氧隔离结构包括氧阻隔层，其在制造和/或操作存储器件期间将电阻性开关材料与电阻式存储器件的其它部分隔离。另一种这样的氧隔离结构包括牺牲层，其在存储器件的制造和/或操作期间与向电阻开关材料迁移的不想要的氧化反应。

46. 发明申请

US20140377931A1 Metal Aluminum Nitride Embedded Resistors for Resistive Random Memory Access Cells 有权
公开(公告)号：US20140377931A1
公开(公告)日：2014-12-25
申请号：US14480025
申请日：2014-09-08
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Mihir Tendulkar , Randall J. Higuchi , Chien-Lan Hsueh
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/165 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625
摘要： Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and resistive switching layer connected in series. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state, thereby preventing over-programming. The embedded resistor includes aluminum, nitrogen, and one or more additional metals (other than aluminum). The concentration of each component is controlled to achieve desired resistivity and stability of the embedded resistor. In some embodiments, the resistivity ranges from 0.1 Ohm-centimeter to 40 Ohm-centimeter and remains substantially constant while applying an electrical field of up 8 mega-Volts/centimeter to the embedded resistor. The embedded resistor may be made from an amorphous material, and the material is operable to remain amorphous even when subjected to typical annealing conditions.

47. 发明申请

US20140361235A1 Nonvolatile Resistive Memory Element With A Metal Nitride Containing Switching Layer 审中-公开
标题翻译：具有包含开关层的金属氮化物的非易失性电阻性存储元件
公开(公告)号：US20140361235A1
公开(公告)日：2014-12-11
申请号：US14469282
申请日：2014-08-26
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , B82Y10/00 , H01L27/2409 , H01L27/2463 , H01L45/10 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A nonvolatile resistive memory element has a novel variable resistance layer that includes a metal nitride, a metal oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof. One method of forming the novel variable resistance layer comprises an interlayer deposition procedure, in which metal oxide layers are interspersed with metal nitride layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming the novel variable resistance layer comprises an intralayer deposition procedure, in which various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, a metal oxide is deposited, nitridized, and annealed to form the variable resistance layer or a metal nitride is deposited, oxidized, and annealed to form the variable resistance layer.
摘要翻译：非易失性电阻存储元件具有新颖的可变电阻层，其包括金属氮化物，金属氧化物氮化物，二金属氧化物氮化物或其多层叠层。形成新颖的可变电阻层的一种方法包括层间沉积程序，其中金属氧化物层散布有金属氮化物层，然后通过退火工艺转变成基本均匀的层。形成新型可变电阻层的另一种方法包括层间沉积程序，其中各种ALD工艺顺序交错以形成金属氧化物 - 氮化物层。或者，金属氧化物被沉积，氮化和退火以形成可变电阻层，或者金属氮化物被沉积，氧化和退火以形成可变电阻层。

48. 发明申请

US20140353573A1 METHODS AND SYSTEMS TO REDUCE LOCATION-BASED VARIATIONS IN SWITCHING CHARACTERISTICS OF 3D RERAM ARRAYS 有权
标题翻译：减少三维雷达阵列切换特性的基于位置变化的方法与系统
公开(公告)号：US20140353573A1
公开(公告)日：2014-12-04
申请号：US14462374
申请日：2014-08-18
申请人： SANDISK 3D LLC
发明人： Pankaj Kalra , Chandrasekhar Gorla , Masaaki Higashitani
IPC分类号： H01L27/24 , H01L21/3215 , H01L21/3205 , H01L49/02 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2409 , H01L28/20 , H01L29/78642 , H01L31/0547 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/16 , Y02E10/52
摘要： Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.
摘要翻译：描述了用于减少存储器阵列内的存储器单元的开关特性的基于位置的变化的方法。在一些情况下，可以设置每个存储单元内的嵌入式电阻器的电阻以减小存储器阵列内的存储单元的串联电阻的总体变化。例如，与远近位相关联的嵌入式电阻器可以被设置为比与近近位相关联的嵌入式电阻器更低的电阻。嵌入式电阻器可以包括存储器单元内的多晶硅层。可以使用选择性离子注入来降低存储器阵列的特定区域内的存储器单元的嵌入式电阻器电阻并且在存储器阵列内形成两个或更多个不同的嵌入式电阻器组。

49. 发明申请

US20140346433A1 MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：US20140346433A1
公开(公告)日：2014-11-27
申请号：US14456158
申请日：2014-08-11
申请人： SanDisk 3D LLC
发明人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。提供了许多其他方面。

50. 发明授权

US08895949B2 Nonvolatile memory device using a varistor as a current limiter element 有权
公开(公告)号：US08895949B2
公开(公告)日：2014-11-25
申请号：US14176882
申请日：2014-02-10
申请人： SanDisk 3D LLC , Kabushiki Kaisha Toshiba
发明人： Mihir Tendulkar , Imran Hashim , Yun Wang
IPC分类号： H01L29/02 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1616
摘要： Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In some embodiments, the current limiting component comprises a varistor that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

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