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41. 发明授权

US09437301B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US09437301B2
公开(公告)日：2016-09-06
申请号：US14669407
申请日：2015-03-26
申请人： Kabushiki Kaisha Toshiba
发明人： Masanobu Shirakawa
IPC分类号： G11C16/26 , G11C16/04 , G11C16/08 , G11C16/16 , G11C5/06 , G11C29/02 , G11C29/00 , G11C16/02 , G11C29/04 , G11C5/02 , G11C16/10 , G11C16/00 , G11C29/12 , G11C29/44
CPC分类号： G11C16/26 , G11C5/02 , G11C5/06 , G11C16/00 , G11C16/02 , G11C16/0408 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C29/025 , G11C29/04 , G11C29/50004 , G11C29/789 , G11C2029/1202 , G11C2029/4402 , G11C2213/75
摘要： According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings that shares a plurality of word lines connected to a plurality of memory cells, respectively. The memory region is disposed to one of the plurality of physical blocks. Each of the plurality of string units configures a first logical block, and when the first logical block is failed, information of the first failed logical block is stored in a first region of the memory region.

42. 发明授权

US09424929B1 Memory system and memory control method 有权
标题翻译：内存系统和内存控制方法
公开(公告)号：US09424929B1
公开(公告)日：2016-08-23
申请号：US14848829
申请日：2015-09-09
申请人： Kabushiki Kaisha Toshiba
发明人： Ryo Yamaki , Masanobu Shirakawa
IPC分类号： G11C16/04 , G11C16/08 , G11C16/10 , G11C16/26
CPC分类号： G11C16/08 , G11C7/1006 , G11C16/10 , G11C16/26 , G11C16/32
摘要： According to an embodiment, a memory system includes: a nonvolatile memory to which data in the unit of I/O data of the first number of bits are capable of being input in parallel, and from which data in the unit of I/O data are capable of being output in parallel; a memory interface; an encoding unit configured to generate the second number of codewords; a decoding unit configured to decode a received word read from the nonvolatile memory; and a control unit configured to link an I/O number to the number of the codeword, inputs, to the encoder, each of the codewords of the data to be input to the nonvolatile memory as the data about the position of the bit having the I/O number corresponding to the codeword, reads the second number of received words from the nonvolatile memory to decode the received words, and, when there is a received word that fails to be decoded, reads the received words again after changing the reading voltage, and decodes the received word.
摘要翻译：根据实施例，存储器系统包括：非易失性存储器，能够并行地输入第一位数的I / O数据单元中的数据，以I / O数据为单位的数据能够并行输出; 存储器接口; 编码单元，被配置为生成所述第二数量的码字; 解码单元，被配置为对从非易失性存储器读取的接收字进行解码; 以及控制单元，被配置为将I / O号与所述码字的数量相关联，将要输入到所述非易失性存储器的数据的每个码字输入到所述编码器，作为关于所述位的所述位的数据对应于码字的I / O号，从非易失性存储器中读出第二数量的接收字来解码所接收的字，并且当存在不能解码的接收字时，在更改读取电压之后再次读取接收到的字，并对接收到的字进行解码。

43. 发明授权

US09355731B2 Semiconductor memory device and data erasing method 有权
标题翻译：半导体存储器件和数据擦除方法
公开(公告)号：US09355731B2
公开(公告)日：2016-05-31
申请号：US14637292
申请日：2015-03-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hidehiro Shiga , Masanobu Shirakawa , Kenichi Abe
IPC分类号： G11C16/14 , G11C16/04 , G11C16/34 , G11C16/16
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/3445 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11551
摘要： A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein.
摘要翻译：半导体存储器件包括存储单元阵列，其包括在衬底上方的多组存储单元，所述组包括第一组和第二组，第一组和第二组中的每一个包括第一存储器串和第二存储器串，所述第一存储器串包括设置在第一层中的第一存储单元，所述第二存储器串包括设置在所述第一层上的第二层中的第二存储单元，以及控制器，被配置为对所述存储单元执行擦除操作，擦除操作包括对存储器单元的验证操作，以逐层确定存储器单元是否不能擦除存储在其中的数据。

44. 发明授权

US09269445B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09269445B1
公开(公告)日：2016-02-23
申请号：US14634873
申请日：2015-03-01
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichi Abe , Masanobu Shirakawa
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C2211/5648
摘要： A semiconductor memory device includes a first set of memory cells commonly connected to a first word line, a second set of memory cells commonly connected to a second word line, and a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines. The writing operation includes a coarse program operation and a fine program operation and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes starting the following operations in order: (1) the coarse program operation on the first set of memory cells; (2) the coarse program operation on the second set of memory cells; (3) the fine program operation on the first set of memory cells; and (4) the fine program operation on the second set of memory cells.
摘要翻译：半导体存储器件包括共同连接到第一字线的第一组存储器单元，公共连接到第二字线的第二组存储器单元，以及被配置为对存储器单元执行写入操作的控制电路，包括控制施加到第一和第二字线的电压。写入操作包括粗略编程操作和精细编程操作，并且控制电路在单次写入操作中对第一和第二组存储器单元执行写入操作，其包括依次开始以下操作：（1）粗略程序对第一组记忆单元进行操作; （2）第二组存储器单元上的粗略编程操作; （3）对第一组存储单元进行精细编程操作; 和（4）对第二组存储器单元的精细编程操作。

45. 发明授权

US09129683B2 High performance semiconductor memory device that has different page addresses allotted to multiple bits of memory cells 有权
标题翻译：具有分配给多个存储单元的不同页面地址的高性能半导体存储器件
公开(公告)号：US09129683B2
公开(公告)日：2015-09-08
申请号：US14015971
申请日：2013-08-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masaki Unno , Naoya Tokiwa , Masanobu Shirakawa
IPC分类号： G06F3/06 , G11C16/10 , G11C11/56 , G11C16/30
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/30
摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells, each memory cell configured to store plural bits of data, and a controller. The controller is configured to execute a write operation on the memory cells such that user data are written in at least one of the plural bits of data and prescribed data are written in the remaining bits of the plural bits of data. As a result, the number of bits of user data stored in the memory cells is less than the number of plural bits of data that each memory cell is configured to store.
摘要翻译：半导体存储器件包括具有多个存储单元的存储单元阵列，每个存储器单元被配置为存储多个数据位，以及控制器。控制器被配置为对存储器单元执行写入操作，使得用户数据被写入数据的多个位中的至少一个，并且规定的数据被写入多个数据位的剩余位中。结果，存储在存储器单元中的用户数据的位数小于每个存储器单元被配置为存储的多个数据位的数量。

46. 发明授权

US08976602B2 Non-volatile semiconductor device 有权
标题翻译：非易失性半导体器件
公开(公告)号：US08976602B2
公开(公告)日：2015-03-10
申请号：US13783363
申请日：2013-03-03
申请人： Kabushiki Kaisha Toshiba
发明人： Hidehiro Shiga , Masanobu Shirakawa
IPC分类号： G11C16/04 , G11C16/34 , G11C16/08 , G11C16/14 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/3436 , G11C16/3445 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.
摘要翻译：非易失性半导体器件包括第一和第二选择晶体管; 堆叠在衬底上方的多个存储单元; 连接到多个存储器单元的控制栅极的多个字线; 选择各自连接到所述选择晶体管之一的栅极的栅极线; 连接到第一选择晶体管的位线; 连接到第二选择晶体管的源极线; 以及控制电路，被配置为执行包括擦除操作和验证操作的擦除循环。控制电路根据擦除循环重复次数增加擦除电压。

47. 发明授权

US08958247B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08958247B2
公开(公告)日：2015-02-17
申请号：US13782847
申请日：2013-03-01
申请人： Kabushiki Kaisha Toshiba
发明人： Norichika Asaoka , Masanobu Shirakawa
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5621 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3445 , G11C29/04 , G11C29/44 , G11C29/785 , G11C29/789 , G11C29/832
摘要： A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.
摘要翻译：半导体存储器件包括具有第一和第二选择性晶体管的存储器串，每个选择晶体管包括电荷存储层和控制栅极，包括电荷存储层和控制栅极的背栅晶体管和连接到每个的存储单元晶体管并且连接到第一和第二选择晶体管之间的串联的背栅晶体管。在存储单元晶体管中存在任何缺陷的情况下，通过将电荷存储在第一和第二选择晶体管和背栅晶体管中的至少一个的电荷存储层中来表示缺陷。

48. 发明申请

US20140269084A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20140269084A1
公开(公告)日：2014-09-18
申请号：US14292440
申请日：2014-05-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Norichika ASAOKA , Masanobu Shirakawa , Kiyotaro Itagaki
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/10 , G11C2213/71 , H01L27/1157 , H01L27/11582
摘要： When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period.The second time period is different from the first time period.
摘要翻译：当执行数据擦除操作时，控制电路至少在漏极侧选择晶体管和源极侧选择晶体管中的任何一个处产生正空穴，并且将正空穴提供给存储器体的主体以提高主体的电压的存储器串到第一电压。然后，在第一时间段期间，将多个字线中的第一电压小于第一电压的电压施加到第一字线。此外，在第二时间段期间，它将小于第一电压的电压施加到与第一字线不同的第二字线。第二时间段与第一时间段不同。

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