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1. 发明授权

US09633745B2 Semiconductor memory device 有权
公开(公告)号：US09633745B2
公开(公告)日：2017-04-25
申请号：US15185671
申请日：2016-06-17
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Abe , Masanobu Shirakawa , Mizuho Yoshida , Takuya Futatsuyama
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56 , G11C16/10 , G11C16/32 , G11C16/08 , G11C16/16 , G11C29/42
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/32 , G11C16/3445 , G11C16/3481 , G11C29/42 , G11C2211/5621 , G11C2211/5648
摘要： A semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

2. 发明授权

US09214238B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09214238B2
公开(公告)日：2015-12-15
申请号：US14474307
申请日：2014-09-02
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takuya Futatsuyama , Masanobu Shirakawa , Kenichi Abe
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： A semiconductor memory device includes first to fourth memory cells that are stacked above a semiconductor substrate, first to fourth word lines that are connected to gates of the first to fourth memory cells, respectively, and a row decoder that applies voltages to the first to fourth word lines. The row decoder applies a first programming voltage to the first word line during a write operation performed on the first memory cell, applies the first programming voltage to the second word line during a write operation performed on the second memory cell, applies a second programming voltage to the third word line during a write operation performed on the third memory cell, and applies the second programming voltage to the fourth word line during a write operation performed on the fourth memory cell. The second programming voltage is higher than the first programming voltage.
摘要翻译：一种半导体存储器件包括堆叠在半导体衬底之上的第一至第四存储单元，分别连接到第一至第四存储单元的栅极的第一至第四字线以及向第一至第四存储单元施加电压的行解码器字线。行解码器在对第一存储单元执行的写入操作期间向第一字线施加第一编程电压，在对第二存储单元执行的写入操作期间将第一编程电压施加到第二字线，施加第二编程电压在对第三存储器单元执行的写入操作期间将第二编程电压施加到第四字线，并且在对第四存储器单元执行的写入操作期间将第二编程电压施加到第四字线。第二编程电压高于第一编程电压。

3. 发明授权

US08772940B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08772940B2
公开(公告)日：2014-07-08
申请号：US13762787
申请日：2013-02-08
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Abe , Takuya Futatsuyama , Jumpei Sato
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/823871 , H01L21/823892 , H01L23/485 , H01L23/528 , H01L23/5283 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.
摘要翻译：在半导体器件中，第一接触扩散层位于第一阱中，以连接到第一阱，并且在第一阱中的第一晶体管的沟道宽度方向上延伸。第一接触扩散层位于第一阱中，以与第一阱电连接并在第一晶体管的沟道长度方向上延伸。第一接触扩散层的第一接触部具有从基板的上方观察时的通道宽度方向的直径大于沟道长度方向的直径的形状。在第二接触扩散层上的第二接触具有沟道宽度方向的直径小于第一接触部的直径的形状，并且当从第一接触扩散层观察时，通道长度方向上的直径几乎等于第一接触的直径在基材之上。布线通过第二触点与第一晶体管电连接。

4. 发明授权

US09892040B2 Semiconductor memory device 有权
公开(公告)号：US09892040B2
公开(公告)日：2018-02-13
申请号：US14841459
申请日：2015-08-31
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa , Takuya Futatsuyama , Kenichi Abe
IPC分类号： G06F12/08 , G06F12/0811 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/30 , G11C11/56 , G11C8/08 , G11C29/02 , G06F12/0868 , G11C16/26 , G11C16/16 , G11C29/12
CPC分类号： G06F12/0811 , G06F12/0868 , G06F2212/283 , G11C8/08 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/30 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A semiconductor memory device includes: a memory cell array including memory strings, one of the memory strings including memory cells; word lines commonly connected to the memory strings; and a controller configured to execute a write operation and a read operation on a page, the page being stored in memory cells connected to one of the word lines. The controller is configured to measure a cell current flowing in the memory string, and adjust a write voltage applied to a word line, based on a result of the cell current.

5. 发明授权

US09361988B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09361988B2
公开(公告)日：2016-06-07
申请号：US14469522
申请日：2014-08-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa , Takuya Futatsuyama , Kenichi Abe , Hiroshi Nakamura , Keisuke Yonehama , Atsuhiro Sato , Hiroshi Shinohara , Yasuyuki Baba , Toshifumi Minami
IPC分类号： G11C16/04 , G11C16/14
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3445 , G11C29/42 , H01L27/1157 , H01L27/11582
摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
摘要翻译：半导体存储器件包括第一存储器单元，第一存储单元上方的第二存储器单元，电连接到第一存储单元的栅极的第一字线，与第二存储单元的栅极电连接的第二字线，以及对第一和第二存储单元执行擦除操作的控制单元。在擦除操作期间，控制单元向第二字线施加第一电压到第一字线和高于第一电压的第二电压。

6. 发明授权

US09257183B2 Semiconductor storage device having nand-type flash memory 有权
标题翻译：具有n型闪存的半导体存储装置
公开(公告)号：US09257183B2
公开(公告)日：2016-02-09
申请号：US14474043
申请日：2014-08-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichi Abe , Takuya Futatsuyama , Masanobu Shirakawa
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26 , G11C16/32
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32
摘要： A semiconductor storage device includes a plurality of memory cell transistors that are connected to each other in series, a plurality of word lines that are connected to the plurality of memory cell transistors, and a control circuit. The control circuit applies a first potential to a selected one of the plurality of word lines. The control circuit applies a second potential that is higher than the first potential to the word lines that are not selected at different timings before the first potential is applied to the selected word line.
摘要翻译：半导体存储装置包括串联连接的多个存储单元晶体管，连接到多个存储单元晶体管的多条字线以及控制电路。控制电路将第一电位施加到多个字线中的所选择的一个字线。在将第一电位施加到所选择的字线之前，控制电路将不高于第一电位的第二电位施加到在不同定时未被选择的字线。

7. 发明授权

US09799403B2 Semiconductor memory device 有权
公开(公告)号：US09799403B2
公开(公告)日：2017-10-24
申请号：US15174849
申请日：2016-06-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa , Takuya Futatsuyama , Kenichi Abe , Hiroshi Nakamura , Keisuke Yonehama , Atsuhiro Sato , Hiroshi Shinohara , Yasuyuki Baba , Toshifumi Minami
IPC分类号： G11C16/04 , G11C16/14 , H01L27/1157 , H01L27/11582 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/42 , G11C16/34
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3445 , G11C29/42 , H01L27/1157 , H01L27/11582
摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

8. 发明授权

US09355731B2 Semiconductor memory device and data erasing method 有权
标题翻译：半导体存储器件和数据擦除方法
公开(公告)号：US09355731B2
公开(公告)日：2016-05-31
申请号：US14637292
申请日：2015-03-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hidehiro Shiga , Masanobu Shirakawa , Kenichi Abe
IPC分类号： G11C16/14 , G11C16/04 , G11C16/34 , G11C16/16
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/3445 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11551
摘要： A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein.
摘要翻译：半导体存储器件包括存储单元阵列，其包括在衬底上方的多组存储单元，所述组包括第一组和第二组，第一组和第二组中的每一个包括第一存储器串和第二存储器串，所述第一存储器串包括设置在第一层中的第一存储单元，所述第二存储器串包括设置在所述第一层上的第二层中的第二存储单元，以及控制器，被配置为对所述存储单元执行擦除操作，擦除操作包括对存储器单元的验证操作，以逐层确定存储器单元是否不能擦除存储在其中的数据。

9. 发明授权

US09269445B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09269445B1
公开(公告)日：2016-02-23
申请号：US14634873
申请日：2015-03-01
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichi Abe , Masanobu Shirakawa
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C2211/5648
摘要： A semiconductor memory device includes a first set of memory cells commonly connected to a first word line, a second set of memory cells commonly connected to a second word line, and a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines. The writing operation includes a coarse program operation and a fine program operation and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes starting the following operations in order: (1) the coarse program operation on the first set of memory cells; (2) the coarse program operation on the second set of memory cells; (3) the fine program operation on the first set of memory cells; and (4) the fine program operation on the second set of memory cells.
摘要翻译：半导体存储器件包括共同连接到第一字线的第一组存储器单元，公共连接到第二字线的第二组存储器单元，以及被配置为对存储器单元执行写入操作的控制电路，包括控制施加到第一和第二字线的电压。写入操作包括粗略编程操作和精细编程操作，并且控制电路在单次写入操作中对第一和第二组存储器单元执行写入操作，其包括依次开始以下操作：（1）粗略程序对第一组记忆单元进行操作; （2）第二组存储器单元上的粗略编程操作; （3）对第一组存储单元进行精细编程操作; 和（4）对第二组存储器单元的精细编程操作。

10. 发明授权

US09704570B2 Semiconductor memory device and memory system 有权
公开(公告)号：US09704570B2
公开(公告)日：2017-07-11
申请号：US15063886
申请日：2016-03-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichi Abe , Masanobu Shirakawa
IPC分类号： G11C16/26 , G11C16/08 , G11C5/06 , G11C16/24 , G11C11/56 , G11C16/04 , G11C16/34 , G11C5/02
CPC分类号： G11C11/5642 , G11C5/02 , G11C5/06 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2213/71 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, and first and second bit lines. The first and second bit lines are electrically connected to one ends of the first and second memory cells, respectively. In retry reading, a voltage applied to the first bit line is different from a voltage applied to the second bit line.

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