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41. 发明授权

US06433585B1 Overvoltage-tolerant interface for integrated circuits 有权
标题翻译：集成电路的过压容限接口
公开(公告)号：US06433585B1
公开(公告)日：2002-08-13
申请号：US09401145
申请日：1999-09-22
申请人： Rakesh H. Patel , John E. Turner , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , Wilson Wong
IPC分类号： H03K19094
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
摘要翻译：一种用于直接与在输入/输出驱动器的电源电压（817）之上的焊盘（820）处的电压直接接口的输入/输出驱动器。这可能被称为“过电压条件”。例如，如果电源电压为3.3V，则可以在输入/输出驱动器的焊盘处提供5V电压信号。输入/输出驱动器将容忍该电压电平并防止漏电流路径。这将提高集成电路的性能，可靠性和使用寿命。输入/输出驱动器包括用于防止泄漏电流路径的阱偏压发生器（1002）。

42. 发明授权

US6107854A Variable speed path circuit and method 失效
标题翻译：变速路径电路及方法
公开(公告)号：US6107854A
公开(公告)日：2000-08-22
申请号：US62379
申请日：1998-04-17
申请人： Wilson Wong , John E. Turner , Thomas H. White , Rakesh H Patel
发明人： Wilson Wong , John E. Turner , Thomas H. White , Rakesh H Patel
IPC分类号： H03K5/00 , H03K19/003 , H03K19/017 , H03K19/0185 , H03H11/26
CPC分类号： H03K19/00384 , H03K19/01721 , H03K19/018585 , H03K2005/00078
摘要： A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.
摘要翻译：速度路径电路包括参考电路和可调节的驱动部件，其可以被接通或关断以改变速度路径，以便满足电路的最小延迟规范。在一个实施例中，使用一个或多个差分放大器来检测示例电路元件的强度并产生参考信号。可选实施例包括用于断开参考电路以避免任何直流电流消耗的机构。本发明可以用于广泛的集成电路中，并且还可以用在可编程逻辑器件（PLD）中。参考电路可以通过使用可编程逻辑元件与电源断开连接。

43. 发明申请

US20100119024A1 METHOD AND APPARATUS FOR MULTI-MODE CLOCK DATA RECOVERY 有权
标题翻译：用于多模式时钟数据恢复的方法和装置
公开(公告)号：US20100119024A1
公开(公告)日：2010-05-13
申请号：US12688617
申请日：2010-01-15
申请人： Sergey Y. Shumarayev , Rakesh H. Patel , Wilson Wong , Tim T. Hoang
发明人： Sergey Y. Shumarayev , Rakesh H. Patel , Wilson Wong , Tim T. Hoang
IPC分类号： H04L7/00
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.
摘要翻译：所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。（CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。

44. 发明授权

US07680232B2 Method and apparatus for multi-mode clock data recovery 失效
标题翻译：多模时钟数据恢复的方法和装置
公开(公告)号：US07680232B2
公开(公告)日：2010-03-16
申请号：US11040342
申请日：2005-01-21
申请人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim T Hoang
发明人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim T Hoang
IPC分类号： H04L7/00 , H03D3/24
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.
摘要翻译：所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。（CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。

45. 发明授权

US07557615B1 High-speed serial data transmitter architecture 有权
标题翻译：高速串行数据发射机架构
公开(公告)号：US07557615B1
公开(公告)日：2009-07-07
申请号：US12069353
申请日：2008-02-08
申请人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
发明人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
IPC分类号： H03K19/094 , H03K3/00
CPC分类号： H03K19/17744 , H03K19/17732 , H04B1/005 , H04L25/028
摘要： Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.
摘要翻译： PLD上的串行数据发射机电路包括许多功能，使得发射机能够在广泛的电路条件下支持许多不同的通信协议。发射机可以包括的特征的示例是（1）可选强度和极性的多个预加重电路，（2）可选择的VOD，（3）可选择的转换速率，（4）可校准终止，（5）可选择的共模电压，和（6）电气空闲模式。

46. 发明授权

US07304494B2 Methods and apparatus to DC couple LVDS driver to CML levels 有权
标题翻译：将LVDS驱动程序直接耦合到CML级别的方法和设备
公开(公告)号：US07304494B2
公开(公告)日：2007-12-04
申请号：US11098832
申请日：2005-04-04
申请人： Wilson Wong , Tim T Hoang , Sergey Y Shumarayev , Rakesh H Patel , Simardeep Maangat
发明人： Wilson Wong , Tim T Hoang , Sergey Y Shumarayev , Rakesh H Patel , Simardeep Maangat
IPC分类号： H03K17/16
CPC分类号： H03K19/017545
摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.
摘要翻译：为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。此外，电阻下拉可以是可编程的。这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

47. 发明授权

US6147511A Overvoltage-tolerant interface for integrated circuits 失效
标题翻译：集成电路的过压容限接口
公开(公告)号：US6147511A
公开(公告)日：2000-11-14
申请号：US863886
申请日：1997-05-27
申请人： Rakesh H. Patel , John E. Turner , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , Wilson Wong
IPC分类号： H01L27/04 , G11C5/14 , H01L21/822 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an "overvoltage condition. " For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
摘要翻译：一种用于直接与在输入/输出驱动器的电源电压（817）之上的焊盘（820）处的电压直接接口的输入/输出驱动器。这可以被称为“过电压状态”。例如，如果电源电压为3.3V，则可以在输入/输出驱动器的焊盘处提供5V电压信号。输入/输出驱动器将容忍该电压电平并防止漏电流路径。这将提高集成电路的性能，可靠性和使用寿命。输入/输出驱动器包括用于防止泄漏电流路径的阱偏压发生器（1002）。

48. 发明授权

US6025737A Circuitry for a low internal voltage integrated circuit 失效
标题翻译：低内部集成电路的电路
公开(公告)号：US6025737A
公开(公告)日：2000-02-15
申请号：US863876
申请日：1997-05-27
申请人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
IPC分类号： H03K19/00 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315 , H03K19/0027 , H03K19/018521
摘要： A technique and circuitry for interfacing an integrated circuit manufactured using technology compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, the integrated circuit is fabricated using technology compatible with an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage. The input and output signals to and from the integrated circuit will be compatible with the external supply level. The integrated circuit may include a voltage down converter (1330) and level shifter (1317).
摘要翻译：一种技术和电路，用于使用与一个电压电平兼容的技术制造的集成电路与与不同电压电平兼容的其他集成电路进行接口。特别地，使用与内部电源电压相兼容的技术来制造集成电路。在外部，集成电路将与外部电源电压接口，高于内部电源电压。来往于集成电路的输入和输出信号将与外部电源电平兼容。集成电路可以包括电压降压转换器（1330）和电平移位器（1317）。

49. 发明授权

US08836443B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08836443B2
公开(公告)日：2014-09-16
申请号：US13617347
申请日：2012-09-14
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H01L23/66 , H03B5/08 , H03C3/22 , H01F27/29 , H03B5/12 , H01F27/28 , H01F21/12
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

50. 发明授权

US08406258B1 Apparatus and methods for low-jitter transceiver clocking 有权
标题翻译：低抖动收发器时钟的装置和方法
公开(公告)号：US08406258B1
公开(公告)日：2013-03-26
申请号：US12752984
申请日：2010-04-01
申请人： Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Sergey Shumarayev , Allen Chan
发明人： Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Sergey Shumarayev , Allen Chan
IPC分类号： H04J3/06
CPC分类号： H03M9/00 , H03K19/1776 , H04J3/047 , H04J3/0685
摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。还公开了其它实施例和特征。

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