专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08248175B2 Oscillator with external voltage control and interpolative divider in the output path 有权
标题翻译：具有外部电压控制的振荡器和输出路径中的内插分压器
公开(公告)号：US08248175B2
公开(公告)日：2012-08-21
申请号：US12981854
申请日：2010-12-30
申请人： Susumu Hara
发明人： Susumu Hara
IPC分类号： H03B1/00 , H03B5/00 , H03B19/00 , H03L7/00 , H03L7/16 , H03L7/18
CPC分类号： H03L7/16 , G06F1/08
摘要： An oscillator output is controlled from an external voltage control terminal using an interpolative divider as a frequency modulator. The oscillator includes a reference clock generator, analog to digital converter, and an interpolative divider. Nominal output frequency is determined by the frequency of the reference clock and the nominal divide value of the interpolative divider. The divide value is changed according to the voltage control input value which is converted to a digital value via an analog to digital converter. Multiple interpolative dividers may be coupled to the single reference clock generator and each have a voltage control input and analog to digital converter.
摘要翻译：使用内插分压器作为频率调制器，从外部电压控制端子控制振荡器输出。振荡器包括参考时钟发生器，模数转换器和内插分压器。标称输出频率由参考时钟的频率和内插分频器的额定分频值决定。分频值根据经由模数转换器转换为数字值的电压控制输入值而改变。多个内插分频器可以耦合到单个参考时钟发生器，并且每个具有电压控制输入和模数转换器。

42. 发明申请

US20080290953A1 System and Method for Generating LO Frequencies with Phase Locking in 2 Steps 有权
标题翻译：用2阶段锁相生成LO频率的系统和方法
公开(公告)号：US20080290953A1
公开(公告)日：2008-11-27
申请号：US11753999
申请日：2007-05-25
申请人： Christoph Sandner , Staffan Ek , Stefano Marsili
发明人： Christoph Sandner , Staffan Ek , Stefano Marsili
IPC分类号： H03L7/16 , H03L7/08
CPC分类号： H03L7/23 , H04B1/7136 , H04B2001/71362 , H04B2001/71365 , H04L2027/0016 , H04L2027/0057 , H04L2027/0065
摘要： System and method for generating multiple local oscillator signals comprising a first-stage phase-locked loop (PLL) having an input to receive a first reference signal input and having an output to transmit a second reference signal, wherein the second reference signal is an integer or fractional multiple of the first reference signal; and a plurality of second-stage PLLs, each second-stage PLL having an input coupled to the output of the first-stage PLL and receiving the second reference signal, and each second-stage PLL having an output for transmitting a local oscillator signal, wherein each of the local oscillator signals is an integer multiple of the second reference signal.
摘要翻译：用于产生多个本地振荡器信号的系统和方法，包括具有用于接收第一参考信号输入并具有传输第二参考信号的输出的输入的第一级锁相环（PLL），其中所述第二参考信号是整数或第一参考信号的分数倍; 和多个第二级PLL，每个第二级PLL具有耦合到第一级PLL的输出并接收第二参考信号的输入，并且每个第二级PLL具有用于发送本地振荡器信号的输出，其中每个本地振荡器信号是第二参考信号的整数倍。

43. 发明申请

US20080218281A1 Anodically Bonded Cell, Method for Making Same and Systems Incorporating Same 审中-公开
标题翻译：阳极粘结电池，制造相同的方法和包含相同的系统
公开(公告)号：US20080218281A1
公开(公告)日：2008-09-11
申请号：US12121876
申请日：2008-05-16
申请人： Steven Alan Lipp , Joseph H. Abeles , Alan Michael Braun , Sterling Eduard McBride , John P. Riganati , Ralph Doud Whaley , Peter J. Zanzucchi
发明人： Steven Alan Lipp , Joseph H. Abeles , Alan Michael Braun , Sterling Eduard McBride , John P. Riganati , Ralph Doud Whaley , Peter J. Zanzucchi
IPC分类号： H01S1/06 , H03L7/16 , H01L21/30
CPC分类号： G04F5/14
摘要： A cell suitable for use with an atomic clock and a method for making the same, the cell including: a silicon wafer having a recess formed therein; at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon sealing the recess; and, an alkali metal containing component and buffer gas contained in the recess. The method includes: providing a silicon wafer; forming a cavity through the silicon wafer; introducing an alkali metal containing component and buffer gas into the cavity; and, anodically bonding at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon to the wafer to close the cavity.
摘要翻译：适用于原子钟的电池及其制造方法，所述电池包括：形成有凹部的硅晶片; 至少一种无定形硅酸盐部件，其离子迁移率和温度膨胀系数近似于密封凹部的硅的非晶硅酸盐部件; 以及包含在所述凹部中的含碱金属成分和缓冲气体。该方法包括：提供硅晶片; 通过硅晶片形成空腔; 将含碱金属的组分和缓冲气体引入所述空腔中; 并且将具有大约硅的离子迁移率和温度膨胀系数的至少一种无定形硅酸盐构件阳极结合到晶片上以封闭空腔。

44. 发明授权

US06973136B2 Radio communications apparatus 失效
标题翻译：无线通信装置
公开(公告)号：US06973136B2
公开(公告)日：2005-12-06
申请号：US09893854
申请日：2001-06-28
申请人： Noriharu Kojima , Hideki Watanabe , Yasunobu Akaoka , Junichi Takada
发明人： Noriharu Kojima , Hideki Watanabe , Yasunobu Akaoka , Junichi Takada
IPC分类号： H04L27/20 , H03C3/09 , H03D7/16 , H03L7/16 , H04B1/04 , H04B1/40 , H04L27/36 , H04L23/02 , H04L5/12
CPC分类号： H03C3/0966 , H03D7/165 , H03L7/16 , H03L2207/12 , H04B1/403
摘要： A phase comparator (106) compares a phase of the output signal of the quadrature modulator (104) with the phase of the signal obtained by frequency-converting the output signal of a first VCO (101) via the second VCO (102) and the first mixer (108). A PLL modulator includes a low-pass filter (107) filters a component below a predetermined frequency of the output signal of the phase comparator (106) and supplying the resulting signal to the frequency control terminal of the first VCO (101). The output signal (TS1) of the first VCO (101) is a modulated signal conforming to a modulation system having a constant envelope waveform, while the output signal of the quadrature modulator (104) is input to the first band-pass filter (110) and the output signal (TS2) of the first band-pass filter is a modulated signal conforming to a modulation system accompanied by an amplitude component as information.
摘要翻译：相位比较器（106）将正交调制器（104）的输出信号的相位与通过经由第二VCO（102）对第一VCO（101）的输出信号进行频率转换而获得的信号的相位进行比较，第一混合器（108）。 PLL调制器包括低通滤波器（107）对低于相位比较器（106）的输出信号的预定频率的分量进行滤波，并将得到的信号提供给第一VCO（101）的频率控制端。第一VCO（101）的输出信号（TS 1）是符合具有恒定包络波形的调制系统的调制信号，而正交调制器（104）的输出信号被输入到第一带通滤波器 110），并且第一带通滤波器的输出信号（TS 2）是符合作为信息的伴随振幅分量的调制系统的调制信号。

45. 发明申请

US20050232386A1 Synchronization circuit and synchronization method 有权
标题翻译：同步电路和同步方法
公开(公告)号：US20050232386A1
公开(公告)日：2005-10-20
申请号：US11156473
申请日：2005-06-21
申请人： Kinya Mitsumoto
发明人： Kinya Mitsumoto
IPC分类号： G06F1/06 , G11C11/407 , G11C11/4076 , H03K5/13 , H03L7/00 , H03L7/06 , H03L7/081 , H03L7/087 , H03L7/089 , H03L7/095 , H03L7/099 , H03L7/107 , H03L7/16 , H03L7/191 , H04L7/04
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/087 , H03L7/0891 , H03L7/095 , H03L7/0995 , H03L7/191
摘要： In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the phase from the first pulse. The reference pulse and the first pulse are compared by a first phase comparing circuit, and the reference pulse, second pulse and third pulse are compared by a second phase comparing circuit. A control voltage generating circuit forms a control voltage by giving priority to a comparison output of the second phase comparing circuit against a comparison output of the first phase comparing circuit. Delay time of the first variable delay circuit is controlled after the phases are matched by forming the control voltage with the comparison output of the first phase comparing circuit.
摘要翻译：在同步电路和同步方法中，第一可变延迟电路产生与参考脉冲同步的第一脉冲，在第一脉冲的相位中引出的第二脉冲和相位延迟的第三脉冲从第一脉冲。参考脉冲和第一脉冲通过第一相位比较电路进行比较，并且通过第二相位比较电路比较参考脉冲，第二脉冲和第三脉冲。控制电压产生电路通过优先考虑第二相位比较电路的比较输出与第一相位比较电路的比较输出而形成控制电压。通过用第一相位比较电路的比较输出形成控制电压，在相位匹配之后，控制第一可变延迟电路的延迟时间。

46. 发明申请

US20050218997A1 High performance signal generation 有权
标题翻译：高性能信号发生
公开(公告)号：US20050218997A1
公开(公告)日：2005-10-06
申请号：US10817780
申请日：2004-04-02
申请人： Fang Xu
发明人： Fang Xu
IPC分类号： H03L7/085 , G01R25/00 , G01R25/04 , G01R31/28 , G01R31/317 , G01R31/319 , H03D3/00 , H03D13/00 , H03L7/00 , H03L7/087 , H03L7/091 , H03L7/16
CPC分类号： H03L7/085 , G01R25/04 , G01R31/31709 , G01R31/31922 , H03D13/003 , H03L7/087 , H03L7/091 , H03L7/16
摘要： A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal to produce a measure of phase error. The phase detector can be advantageously used in a frequency synthesizer to produce signals with low phase noise and accurate phase control. Synthesizers of this type can further be used to as building blocks in ATE systems and other electronic systems for generating low jitter clocks and waveforms.
摘要翻译：高性能相位检测器包括用于产生可编程频率和相位的数字参考信号的本地数字振荡器。相位检测器累积数字参考信号和采样输入信号之间的相位差，以产生相位误差的测量。相位检测器可以有利地用在频率合成器中以产生具有低相位噪声和精确相位控制的信号。这种类型的合成器可进一步用作ATE系统和其他用于产生低抖动时钟和波形的电子系统的构建块。

47. 发明申请

US20050104639A1 MODULAR DLL ARCHITECTURE FOR GENERATING MULTIPLE TIMINGS 失效
标题翻译：用于生成多个时间的模块化DLL体系结构
公开(公告)号：US20050104639A1
公开(公告)日：2005-05-19
申请号：US10707067
申请日：2003-11-19
申请人： Darren Anand , Kevin Gorman
发明人： Darren Anand , Kevin Gorman
IPC分类号： G06F1/04 , G11C7/22 , G11C11/407 , H03L7/00 , H03L7/06 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/07 , G11C7/22 , G11C7/222 , H03L7/0814
摘要： A modular Digital Locked Loop (DLL) architecture capable of generating a plurality of multiple phase clock signals, having particular applicability to synchronization of embedded DRAM systems with on chip timing. The architecture comprises a single core frequency locking circuit that includes a delay element with control logic and locking circuitry capable of locking the DLL system clock frequency to an external reference clock, and a plurality of secondary phase locking circuits capable of synchronizing a plurality of internal clock signals to any phase of the external reference clock.
摘要翻译：一种能够产生多个多相时钟信号的模块化数字锁定环（DLL）架构，其特别适用于具有片上定时的嵌入式DRAM系统的同步。该架构包括单核频率锁定电路，其包括具有控制逻辑的延迟元件和能够将DLL系统时钟频率锁定到外部参考时钟的锁定电路，以及能够使多个内部时钟同步的多个次级锁相电路信号到外部参考时钟的任何相位。

48. 发明授权

US06891420B2 Method and apparatus for digital frequency synthesis 有权
标题翻译：数字频率合成方法和装置
公开(公告)号：US06891420B2
公开(公告)日：2005-05-10
申请号：US10036558
申请日：2001-12-21
申请人： Frederick L. Martin , Robert E. Stengel , Jui-Kuo Juan
发明人： Frederick L. Martin , Robert E. Stengel , Jui-Kuo Juan
IPC分类号： H03L7/081 , H03L7/16 , H03L7/22 , H04B1/40 , H04B7/00
CPC分类号： H03L7/22 , H03L7/0812 , H03L7/16
摘要： A digital frequency synthesizer includes one or more reference clocks (104, 1316, 1502A, 1504A, 1506A) optionally coupled through one or more pulse width reducers (106) to one or more main delay lines (108, 702, 1502B, 1504B, 1506B) that include a plurality of output taps (108B-108I, 702B-702E). During at least certain periods of the reference clock (104) a plurality of the output taps are coupled to a common output (130, 1312, 1508), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates (114, 128, 720-724, 1420-1434) that are switched by gating pulses that are received from decoders (148, 150, 1418) via gating signal delay lines (134-146, 704-718, 1404-1416).
摘要翻译：数字频率合成器包括一个或多个参考时钟（104,1316,1502A，1504A，1506A），其可选地通过一个或多个脉冲宽度减法器（106）耦合到一个或多个主延迟线（108,702,1502B ，1504B，1506B），其包括多个输出抽头（108B-108I，702B-702E）。在参考时钟（104）的至少某些时段期间，多个输出抽头耦合到公共输出（130,1312,1508），从而产生具有超过一个或多个频率的频率的频率的输出信号参考时钟。耦合优选地由通过选通脉冲切换的传输门（114,128,720-724,1420-1434）完成，门脉冲经由选通信号延迟线（134-146,704）从解码器（148,150,1418）接收 -718,1404-1416）。

49. 发明申请

US20050018800A1 APPARATUS OF ADJUSTING WOBBLE CLOCK 有权
标题翻译：调整无线时钟的装置
公开(公告)号：US20050018800A1
公开(公告)日：2005-01-27
申请号：US10709022
申请日：2004-04-07
申请人： Yuan-Kun Hsiao
发明人： Yuan-Kun Hsiao
IPC分类号： G11B5/09 , G11B7/00 , G11B7/0045 , G11B7/095 , G11B7/1267 , G11B19/00 , G11B20/10 , G11B20/16 , G11B27/10 , G11B27/24 , H01H47/00 , H03D3/24 , H03D13/00 , H03L7/00 , H03L7/06 , H03L7/08 , H03L7/089 , H03L7/16 , H04B3/46
CPC分类号： G11B27/24 , G11B7/0945 , G11B7/0956 , G11B7/1267 , H03L7/08
摘要： An apparatus for adjusting the phase of a wobble clock including a phase adjusting circuit for receiving a wobble signal and a wobble clock to generate a phase adjusting value, and a frequency divider coupled to the phase adjusting circuit for adjusting the phase of the wobble clock according to the phase adjusting value.
摘要翻译：一种用于调整摆动时钟的相位的装置，包括用于接收摆动信号和摆动时钟以产生相位调整值的相位调整电路，以及耦合到相位调整电路的分频器，用于调整摆动时钟的相位到相位调整值。

50. 发明申请

US20050017772A1 METHOD AND RELATED APPARATUS FOR DECODING INFORMATION CARRIED BY WOBBLE SIGNALS 有权
标题翻译：用于解码由WOBBLE信号承载的信息的方法和相关装置
公开(公告)号：US20050017772A1
公开(公告)日：2005-01-27
申请号：US10709021
申请日：2004-04-07
申请人： Yuan-Kun Hsiao , Luke Wen
发明人： Yuan-Kun Hsiao , Luke Wen
IPC分类号： G11B5/09 , G11B7/00 , G11B7/0045 , G11B7/095 , G11B7/1267 , G11B19/00 , G11B20/10 , G11B20/16 , G11B27/10 , G11B27/24 , H01H47/00 , H03D3/24 , H03D13/00 , H03L7/00 , H03L7/06 , H03L7/08 , H03L7/089 , H03L7/16 , H04B3/46
CPC分类号： G11B27/24 , G11B7/0945 , G11B7/0956 , G11B7/1267 , H03L7/08
摘要： An apparatus for generating a wobble clock includes an operation circuit for receiving a wobble signal and counting cycles of an oscillating signal during a cycle of the wobble signal to derive a cycle value and for comparing the cycle value with a preset cycle value to output a first protection signal, and a phase-locked loop circuit connected to the operation circuit for receiving the wobble signal, the wobble clock and the first protection signal, and determining whether the wobble clock is to be synchronized with the wobble signal according to the first protection signal.
摘要翻译：一种用于产生摆动时钟的装置包括一个操作电路，用于在摆动信号的周期期间接收摆动信号和对振荡信号的周期进行计数以得到一个周期值，并用于将周期值与一个预设的周期值进行比较，以输出第一个保护信号和连接到操作电路的锁相环电路，用于接收摆动信号，摆动时钟和第一保护信号，并根据第一保护信号确定摆动时钟是否与摆动信号同步。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式