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41. 发明授权

US09467251B2 Method and system for forward error correction decoding with parity check for use in low complexity highly-spectrally efficient communications 有权
公开(公告)号：US09467251B2
公开(公告)日：2016-10-11
申请号：US14635736
申请日：2015-03-02
申请人： MagnaCom Ltd.
发明人： Amir Eliaz
IPC分类号： H03M13/00 , H04L1/00 , H04B1/10 , H04L23/02 , H04L27/04 , H04L27/00 , H04L27/02 , H04L25/03 , H04L27/01 , H04L27/36 , H04L7/00 , G06F11/10 , H04B1/16 , H04L1/20 , H04B1/709 , H04B1/04 , H04L25/08 , H04L25/02 , H04L27/38 , H04B17/00 , H04L7/02 , H04B17/15 , H04L7/04 , H04L27/227
CPC分类号： H04L1/0041 , G06F11/10 , H04B1/0475 , H04B1/10 , H04B1/16 , H04B1/709 , H04B17/0085 , H04B17/15 , H04B17/29 , H04B2001/0416 , H04L1/0036 , H04L1/0048 , H04L1/005 , H04L1/0054 , H04L1/203 , H04L1/206 , H04L7/0058 , H04L7/0087 , H04L7/02 , H04L7/042 , H04L23/02 , H04L25/0236 , H04L25/03006 , H04L25/03038 , H04L25/03057 , H04L25/03178 , H04L25/03197 , H04L25/03267 , H04L25/0328 , H04L25/03305 , H04L25/03318 , H04L25/03337 , H04L25/03343 , H04L25/03834 , H04L25/03885 , H04L25/03949 , H04L25/08 , H04L27/00 , H04L27/01 , H04L27/02 , H04L27/04 , H04L27/2278 , H04L27/36 , H04L27/366 , H04L27/368 , H04L27/38 , H04L2025/03369
摘要： A receiver receives an inter-symbol correlated (ISC) signal with information symbols and a corresponding parity symbol. Values of information symbols are estimated utilizing parity samples that are generated from the parity symbols. One or more maximum likelihood (ML) decoding metrics are generated for the information symbols. One or more estimations are generated for the information symbols based on the one or more ML decoding metrics. A parity metric is generated for each of the one or more generated estimations of the information symbols. The parity metric is generated by summing a plurality of values of one of the generated estimations to generate a sum, and wrapping the sum to obtain a parity check value that is within the boundaries of a symbol constellation utilized in generating the information symbols.

42. 发明申请

US20160241384A1 CARRIER SYNCHRONIZATION APPROPRIATE FOR ALM NFC DATA TRANSMISSION 有权
标题翻译：携带者同步适用于ALM NFC数据传输
公开(公告)号：US20160241384A1
公开(公告)日：2016-08-18
申请号：US14918284
申请日：2015-10-20
申请人： Broadcom Corporation
发明人： Manolis Frantzeskakis , Dong-U Lee , Divyanshu Jain , Jianhua Gan , Shengyang Xu
IPC分类号： H04L7/02 , H04H60/29 , H04B5/00
CPC分类号： H04B5/0031 , H04L27/0014 , H04L2027/0026 , H04L2027/0055 , H04L2027/0067
摘要： In some aspects, the disclosure is directed to methods and systems for carrier synchronization in active load modulation for near field communications. A broadcast carrier is received from a remote device and mixed with a locally-generated carrier and modulated data. A carrier synchronization circuit synchronizes the locally-generated carrier with the broadcast carrier based on an identified phase error from a double Cartesian-to-polar mapping of the mixed locally-generated carrier and broadcast carrier. In some implementations, the system also includes a modulation suppression circuit for providing unmodulated carrier signals to the carrier synchronization circuit or suppressing modulation distortion to maintain frequency and phase tracking despite the presence of data.
摘要翻译：在一些方面，本公开涉及用于近场通信的有源负载调制中的载波同步的方法和系统。从远程设备接收广播载波并与本地生成的载波和调制数据混合。载波同步电路基于从混合的本地生成的载波和广播载波的双笛卡尔到极坐标映射的所识别的相位误差，使本地生成的载波与广播载波同步。在一些实现中，该系统还包括用于向载波同步电路提供未调制的载波信号或抑制调制失真的调制抑制电路，以便尽管数据存在而保持频率和相位跟踪。

43. 发明授权

US09407428B2 Reception apparatus, reception method, and program 有权
标题翻译：接收装置，接收方法和程序
公开(公告)号：US09407428B2
公开(公告)日：2016-08-02
申请号：US14498050
申请日：2014-09-26
申请人： Sony Corporation
发明人： Kenichi Kobayashi , Naoto Nagaki , Hiroyuki Kamata , Satoshi Okada
IPC分类号： H04L7/02 , H04L27/26
CPC分类号： H04L7/02 , H04L27/2662 , H04L27/2672 , H04L27/2675 , H04L27/2678 , H04L27/2685
摘要： Provided is a reception apparatus including: a correction unit that corrects phase compensation for each one of multiple phase-compensated segments that are connected one after another, in which the correction unit includes a timing generation unit that, based on a phase of a known signal, generates a timing at which an amount of the phase compensation is initialized, an amount-of-correction generation unit that, based on the phase of the known signal, generates an amount of correction for correcting the amount of the phase compensation, and a phase correction unit that performs phase correction on the phase compensation using the amount of the correction that is generated by the amount-of-correction generation unit.
摘要翻译：提供一种接收装置，包括：校正单元，用于校正相互连接的多个相位补偿段中的每一个的相位补偿，其中校正单元包括定时生成单元，其基于已知信号的相位生成相位补偿量初始化的定时，基于已知信号的相位产生用于校正相位补偿量的校正量的校正量生成单元，以及相位校正单元，其使用由校正量生成单元生成的校正量对相位补偿执行相位校正。

44. 发明授权

US09374250B1 Wireline receiver circuitry having collaborative timing recovery 有权
标题翻译：有线接收器电路具有协作定时恢复
公开(公告)号：US09374250B1
公开(公告)日：2016-06-21
申请号：US14573343
申请日：2014-12-17
申请人： Intel Corporation
发明人： Tawfiq Musah , Gokce Keskin , Ganesh Balamurugan , James E. Jaussi , Bryan K. Casper
IPC分类号： H03H7/30 , H04L25/03 , H04L7/02
CPC分类号： H04L25/03057 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L25/03146 , H04L25/14
摘要： Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.
摘要翻译：一些实施例包括具有用于接收输入信号的输入的装置和方法，用于接收具有不同相位以对输入信号进行采样的时钟信号的附加输入以及具有DFE切片的判决反馈均衡器（DFE）。 DFE片包括多个数据比较器，用于基于输入信号的采样来提供数据信息，以及多个相位误差比较器，以提供与输入信号的采样相关联的相位误差信息。 DFE切片的相位误差比较器的数量不大于DFE切片的数据比较器的数量。

45. 发明授权

US09337996B2 Data recovery circuit 有权
标题翻译：数据恢复电路
公开(公告)号：US09337996B2
公开(公告)日：2016-05-10
申请号：US14859432
申请日：2015-09-21
申请人： FANUC Corporation
发明人： Tomomasa Nakama
IPC分类号： H04L7/00 , H04L7/02
CPC分类号： H04L7/0337 , H04L7/0331
摘要： In a data recovery circuit, the position of an edge is detected from parallel data acquired by oversampling data received through serial communication, the position of a next edge is estimated, the estimated position of the edge is compared with the detected position of the actual edge, and the sampling position of the parallel data is adjusted based on a result of the comparison. As a result, an oversampling clock can be set to a maximum frequency, and accordingly, the precision of the data recovery circuit can be improved.
摘要翻译：在数据恢复电路中，从通过串行通信接收的过采样数据获取的并行数据检测边缘的位置，估计下一边缘的位置，将该边缘的估计位置与实际边缘的检测位置进行比较，并且基于比较的结果来调整并行数据的采样位置。结果，可以将过采样时钟设置为最大频率，因此可以提高数据恢复电路的精度。

46. 发明申请

US20160112186A1 Frequency Planning for Digital Power Amplifier 审中-公开
标题翻译：数字功率放大器频率规划
公开(公告)号：US20160112186A1
公开(公告)日：2016-04-21
申请号：US14977547
申请日：2015-12-21
申请人： Marvell World Trade Ltd.
发明人： Renaldi Winoto
IPC分类号： H04L7/02
CPC分类号： H04L7/02 , H03F3/217 , H03F3/2175 , H03F3/24 , H04B1/04 , H04B1/0458 , H04B2001/0408
摘要： Systems and techniques relating to wireless communication devices and digital power amplifiers include, according to an aspect, an apparatus including: processor electronics; transceiver electronics coupled with the processor electronics, the transceiver electronics including modulation circuitry and a digital power amplifier coupled with the modulation circuitry; a clock source coupled with the transceiver electronics to provide a clock signal from the clock source to the digital power amplifier at a sampling clock frequency; a local oscillator coupled with the transceiver electronics to provide a local oscillator signal from the local oscillator to the modulation circuitry at a local oscillator frequency; and one or more antennas coupled with the digital power amplifier in the transceiver electronics; wherein the local oscillator frequency is an integer multiple of the sampling clock frequency; and wherein a parasitic frequency response of circuitry in the transceiver electronics acts as an implicit out-of-band filter to remove alias signals.
摘要翻译：根据一个方面，与无线通信设备和数字功率放大器有关的系统和技术包括：处理器电子设备; 收发器电子器件与处理器电子器件耦合，收发器电子器件包括调制电路和与调制电路耦合的数字功率放大器; 与收发器电子设备耦合的时钟源，以采样时钟频率从时钟源向数字功率放大器提供时钟信号; 与收发器电子器件耦合的本地振荡器，以本地振荡器频率向本地振荡器提供本地振荡器信号到调制电路; 以及与收发器电子设备中的数字功率放大器耦合的一个或多个天线; 其中本地振荡器频率是采样时钟频率的整数倍; 并且其中所述收发器电路中的电路的寄生频率响应用作隐式带外滤波器以去除别名信号。

47. 发明授权

US09246668B1 Unified control for digital timing recovery and packet processing 有权
标题翻译：统一控制数字定时恢复和数据包处理
公开(公告)号：US09246668B1
公开(公告)日：2016-01-26
申请号：US14205594
申请日：2014-03-12
申请人： MARVELL INTERNATIONAL LTD.
发明人： Mao Yu , Ming Ta Lin , Sergey Timofeev
IPC分类号： H04L7/00 , H04L7/02
CPC分类号： H04L7/0029 , H04L27/2662 , H04L27/2678
摘要： Systems, methods, and other embodiments associated with unified control of timing recovery and packet processing are described. According to one embodiment, a method for performing unified control of timing recovery and packet processing is provided. The method includes sampling a received signal according to an ADC timing signal to produce a sequence of samples. The received signal corresponds to a packet and was transmitted according to a transmit timing signal. The method includes determining a phase offset between the ADC timing signal and the transmit timing signal and identifying, based, at least in part, on the phase offset, a data portion of the sequence of samples that contains data encoded in the received signal. A re-generated sample sequence that adjusts the data portion based on the phase offset is calculated.
摘要翻译：描述了与定时恢复和分组处理的统一控制相关联的系统，方法和其他实施例。根据一个实施例，提供了一种用于执行定时恢复和分组处理的统一控制的方法。该方法包括根据ADC定时信号对接收到的信号进行采样以产生采样序列。接收到的信号对应于分组，并根据发送定时信号发送。该方法包括确定ADC定时信号和发射定时信号之间的相位偏移，并且至少部分地基于相位偏移来识别包含在接收信号中编码的数据的采样序列的数据部分。计算基于相位偏移来调整数据部分的重新生成的采样序列。

48. 发明授权

US09225321B2 Signal synchronizing systems and methods 有权
标题翻译：信号同步系统和方法
公开(公告)号：US09225321B2
公开(公告)日：2015-12-29
申请号：US13172647
申请日：2011-06-29
申请人： Ankur Bal , Anupam Jain
发明人： Ankur Bal , Anupam Jain
IPC分类号： G06F1/12 , G06F1/00 , H03K5/135 , H04L7/02
CPC分类号： H03K5/135 , G06F1/12 , H04L7/0045 , H04L7/02
摘要： Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal.
摘要翻译：公开了信号同步系统和方法。信号同步系统包括顺序逻辑电路，用于接收输入信号并根据时钟信号从输入信号产生多个中间信号。逻辑电路组合中间信号以产生输出信号。信号接收机包括耦合到微控制器的微控制器和信号同步器。信号同步器包括顺序逻辑电路，用于接收来自发射机的输入信号，并且基于时钟信号从所接收的输入信号产生多个中间信号。逻辑电路组合中间信号以产生输出信号。

49. 发明授权

US09209843B2 Fine phase estimation for highly spectrally efficient communications 有权
标题翻译：高频谱高效通信的精细相位估计
公开(公告)号：US09209843B2
公开(公告)日：2015-12-08
申请号：US14537149
申请日：2014-11-10
申请人： MagnaCom Ltd.
发明人： Amir Eliaz
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40 , H04B1/04 , H04B1/10 , H04L23/02 , H04L27/04 , H04L27/00 , H04L27/02 , H04L25/03 , H04L27/01 , H04L27/36 , G06F11/10 , H04B1/16 , H04L1/20 , H04B1/709 , H04L25/08 , H04L1/00 , H04L25/02 , H04L27/38 , H04B17/00 , H04L7/02
CPC分类号： H04L1/0041 , G06F11/10 , H04B1/0475 , H04B1/10 , H04B1/16 , H04B1/709 , H04B17/0085 , H04B17/15 , H04B17/29 , H04B2001/0416 , H04L1/0036 , H04L1/0048 , H04L1/005 , H04L1/0054 , H04L1/203 , H04L1/206 , H04L7/0058 , H04L7/0087 , H04L7/02 , H04L7/042 , H04L23/02 , H04L25/0236 , H04L25/03006 , H04L25/03038 , H04L25/03057 , H04L25/03178 , H04L25/03197 , H04L25/03267 , H04L25/0328 , H04L25/03305 , H04L25/03318 , H04L25/03337 , H04L25/03343 , H04L25/03834 , H04L25/03885 , H04L25/03949 , H04L25/08 , H04L27/00 , H04L27/01 , H04L27/02 , H04L27/04 , H04L27/2278 , H04L27/36 , H04L27/366 , H04L27/368 , H04L27/38 , H04L2025/03369
摘要： A receiver may process a received signal to generate a processed received signal. The receiver may generate, during a sequence estimation process, an estimate of a phase error of the processed received signal. The receiver may generate an estimate of a value of a transmitted symbol corresponding to the received signal based on the estimated phase error. The generation of the estimate of the phase error may comprise generation of one or more phase candidate vectors. The generation of the estimate may comprise calculation of a metric based on the one or more phase candidate vectors. The calculation of the metric may comprise phase shifting the processed received signal based on the estimated phase error resulting in a phase-corrected received signal. The calculation of the metric may comprise calculating a Euclidean distance based on the phase-corrected received signal and one or more symbol candidate vectors.
摘要翻译：接收机可以处理接收的信号以产生经处理的接收信号。接收机可以在序列估计过程期间产生所处理的接收信号的相位误差的估计。接收机可以基于所估计的相位误差来生成对应于接收信号的发送符号的值的估计。产生相位误差的估计可以包括一个或多个相位候选矢量的产生。估计的产生可以包括基于一个或多个相位候选向量的度量的计算。度量的计算可以包括基于导致相位校正的接收信号的估计的相位误差来相移所处理的接收信号。度量的计算可以包括基于相位校正的接收信号和一个或多个符号候选向量来计算欧氏距离。

50. 发明申请

US20150341159A1 NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD 审中-公开
标题翻译：噪声形状的插值器和减法器装置和方法
公开(公告)号：US20150341159A1
公开(公告)日：2015-11-26
申请号：US14817996
申请日：2015-08-04
申请人： STMicroelectronics N.V.
发明人： Steven R. Norsworthy , Jason Rupert Redgrave
IPC分类号： H04L7/00 , H04L7/02
CPC分类号： H04L7/0008 , H03H17/0614 , H03H17/0628 , H03H2218/04 , H04L7/0025 , H04L7/005 , H04L7/02
摘要： An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.
摘要翻译：内插器或抽取器包括在第一和第二时钟域之间的信号路径中的弹性存储元件。弹性元件可以例如是有利地允许采样时钟的短期变化被吸收的FIFO。反馈机制控制基于Δ-Σ调制的模N计数器的采样时钟发生器。与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。

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