专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06829194B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US06829194B2
公开(公告)日：2004-12-07
申请号：US10307283
申请日：2002-12-02
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义用作数据擦除单位的存储单元范围。半导体设备具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作在第一存储器和第二存储体，同时在第一和第二存储体的另一个中进行数据写入或擦除操作。

52. 发明授权

US06512693B2 Semiconductor device that enables simultaneous read and write/erase operation 有权
标题翻译：实现同时读/写/擦除操作的半导体器件
公开(公告)号：US06512693B2
公开(公告)日：2003-01-28
申请号：US09987981
申请日：2001-11-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C1604
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

53. 发明授权

US08760937B2 Semiconductor memory device with bit line charging circuit and control method thereof 有权
标题翻译：具有位线充电电路的半导体存储器件及其控制方法
公开(公告)号：US08760937B2
公开(公告)日：2014-06-24
申请号：US13324413
申请日：2011-12-13
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C7/10
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/24
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array including memory cells, each of which is arranged at a position of between a word line and a bit line, a row decoder, and a bit line control circuit. And when data is to be read out from the memory cell, a charge control circuit controls the gate voltages of a first transistor, a second transistor, a third transistor, and a fourth transistor, respectively, so that the bit line is charged in accordance with a first characteristic obtained by increasing a current driving capacity of the first transistor during a desired period after start of charge of the bit line, and the bit line is then charged in accordance with a second characteristic obtained by returning the current driving capacity of the first transistor to the lower current driving capacity after elapse of the desired period.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，该存储单元阵列包括存储单元，每个存储单元布置在字线和位线之间的位置，行解码器和位线控制电路。并且当从存储单元读出数据时，充电控制电路分别控制第一晶体管，第二晶体管，第三晶体管和第四晶体管的栅极电压，使得位线根据具有通过在位线开始充电之后的期望周期期间增加第一晶体管的电流驱动能力而获得的第一特性，然后根据通过返回位线的电流驱动能力而获得的第二特性对位线进行充电第一晶体管到期望时间过后的较低电流驱动能力。

54. 发明授权

US08406066B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08406066B2
公开(公告)日：2013-03-26
申请号：US13417954
申请日：2012-03-12
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C7/12
CPC分类号： G11C16/3418 , G11C16/26
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and the sense amplifier, a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor, and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元晶体管，字线，行解码器，通过位线确定存储单元晶体管中的数据的读出放大器，串联连接的第一位线钳位晶体管在位线和读出放大器之间，与第一位线钳位晶体管并联连接的第二位线钳位晶体管，其电流驱动能力高于第一位线钳位晶体管的电流驱动能力，以及位线控制电路，在第一位线钳位晶体管和第二位线钳位晶体管之间，在从位线开始充电的预定时间期间使用公共栅极电压，并且当经过预定周期时，仅关断第二位线钳位晶体管。

55. 发明授权

US08385129B2 Semiconductor memory device and control method thereof 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08385129B2
公开(公告)日：2013-02-26
申请号：US13149286
申请日：2011-05-31
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C16/26
CPC分类号： G11C16/3454 , G11C16/3459
摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cells in which data can be rewritable, a plurality of bit lines connected to the plurality of memory cells, and a plurality of sense circuits that are connected to the plurality of bit lines, respectively, sense data written in the memory cells to perform a verify operation with the bit lines charged to first potentials, and charge a bit line, which is connected to a memory cell determined to be defective as a result of the verify operation, to the first potential in the verify operation.
摘要翻译：根据一个实施例，半导体存储器件包括数据可重写的多个存储器单元，连接到多个存储单元的多个位线以及连接到多个位线的多个读出电路分别写入存储单元中的读出数据，以对被充电到第一电位的位线执行验证操作，并且将与作为验证操作的结果确定为有缺陷的存储单元连接的位线充电到验证操作的第一个潜力。

56. 发明授权

US08259502B2 NAND flash memory 有权
标题翻译： NAND闪存
公开(公告)号：US08259502B2
公开(公告)日：2012-09-04
申请号：US12886275
申请日：2010-09-20
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C16/26
摘要： A NAND flash memory having a memory cell array formed of a plurality of blocks including memory cell transistors arranged in a matrix form. The NAND flash memory has a first bit line; a first sense amplifier connected to the first bit line, the first sense amplifier sensing or controlling a potential on the first bit line; a second bit line; and a second sense amplifier connected to the second bit line to sense or control a potential on the second bit line. The NAND flash memory has a first drain side selection gate line; a second drain side selection gate line; a third drain side selection gate line; a fourth drain side selection gate line; a first source side selection gate line; and a second source side selection gate line. The NAND flash memory has a first block; a second block; and a decoder which turns on one of the first and third drain side selection MOS transistors and turns off the other, and which turns on one of the third and fourth drain side selection MOS transistors and turns off the other.
摘要翻译：具有存储单元阵列的NAND闪速存储器，其由包括以矩阵形式布置的存储单元晶体管的多个块组成。 NAND闪存具有第一位线; 连接到第一位线的第一读出放大器，第一读出放大器感测或控制第一位线上的电位; 第二位线以及第二读出放大器，连接到第二位线以感测或控制第二位线上的电位。 NAND闪速存储器具有第一漏极侧选择栅极线; 第二漏极侧选择栅极线; 第三漏极侧选择栅极线; 第四漏极侧选择栅极线; 第一源极选择栅极线; 和第二源极侧选择栅极线。 NAND闪存具有第一块; 第二块以及解码器，其导通第一和第三漏极侧选择MOS晶体管中的一个并且截止另一个，并且其导通第三和第四漏极侧选择MOS晶体管中的一个并且断开另一个。

57. 发明申请

US20110066794A1 SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME 失效
标题翻译：半导体器件及其控制方法
公开(公告)号：US20110066794A1
公开(公告)日：2011-03-17
申请号：US12953598
申请日：2010-11-24
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G06F12/02
CPC分类号： H01L27/115 , G11C29/20
摘要： A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable signal, a second pad for inputting a write enable signal, a third pad for inputting an output enable signal, a fourth pad for inputting an address signal, and a fifth pad for inputting data. The first semiconductor storage device has a sixth pad which is electrically connected to the first pad of the second semiconductor device, and the second semiconductor storage device has a seventh pad which is electrically connected to the first pad of the first semiconductor device.
摘要翻译：一种半导体器件包括一个板，一个位于该板上的第一个半导体存储器件，以及一个位于该板上的第二个半导体存储器件。第一和第二半导体存储装置中的每一个具有用于输入芯片使能信号的第一焊盘，用于输入写使能信号的第二焊盘，用于输入输出使能信号的第三焊盘，用于输入地址信号的第四焊盘，以及用于输入数据的第五个垫。第一半导体存储装置具有电连接到第二半导体器件的第一焊盘的第六焊盘，并且第二半导体存储器件具有电连接到第一半导体器件的第一焊盘的第七焊盘。

58. 发明申请

US20100214837A1 NONVOLATILE SEMICONDUCTOR MEMORY WITH CHARGE STORAGE LAYERS AND CONTROL GATES 有权
标题翻译：具有充电储存层和控制栅的非易失性半导体存储器
公开(公告)号：US20100214837A1
公开(公告)日：2010-08-26
申请号：US12552563
申请日：2009-09-02
申请人： Mario SAKO , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
发明人： Mario SAKO , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G11C16/04 , G11C11/00
CPC分类号： G11C5/147 , G11C16/0483 , G11C16/30
摘要： A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.
摘要翻译：非易失性半导体存储器包括存储单元阵列，位线，第一电压发生器和第二电压发生器。存储单元阵列包括存储单元。每个位线与相应的一个存储单元的电流路径的一端电连接。第一电压发生器，其能够经由第一输出端子向位线提供外部提供的第一电压或通过降低提供的并高于第一电压的第二电压而获得的第三电压，并且其与第一电压一样高第一电压。第二电压发生器，当第一电压发生器降低第二电压以产生第三电压时，能够将通过第二输出端降低第二电压而获得的第四电压提供给位线。

59. 发明申请

US20100214836A1 Semiconductor storage apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US20100214836A1
公开(公告)日：2010-08-26
申请号：US12656999
申请日：2010-02-23
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C5/145 , G11C8/08 , G11C16/08
摘要： A semiconductor storage apparatus has a control circuit. The control circuit deactivates the first and second amplifier circuits, turns off the first, second, fourth and fifth switch circuits, and turns on the third and sixth switch circuits in response to an external signal based on reduction of current dissipation of a power supply which supplies the power supply voltage.
摘要翻译：半导体存储装置具有控制电路。控制电路使第一和第二放大器电路去激活，关断第一，第二，第四和第五开关电路，并且响应于基于电源的电流耗散的减小的外部信号而接通第三和第六开关电路，提供电源电压。

60. 发明授权

US07750727B2 Voltage generating circuit 失效
标题翻译：电压发生电路
公开(公告)号：US07750727B2
公开(公告)日：2010-07-06
申请号：US12260366
申请日：2008-10-29
申请人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
发明人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , H02M3/073 , H02M2001/0025 , H02M2001/0032 , Y02B70/16
摘要： A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.
摘要翻译：用于从输出端子输出电压的电压产生电路具有连接在输出端子与地之间的第一分压电路; 连接在输出端和第一分压电路之间的开关电路; 第一电压检测电路，输出与比较结果对应的第一泵浦信号; 连接在输出端子和地之间的第二分压电路; 第二电压检测电路，其输出与比较结果相对应的第二泵浦信号; 输出从电源电压提升的电压的泵电路; 以及升压电路，其具有一端与第一分压电路的分压电阻连接的电容元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式