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51. 发明授权

US06853509B2 Acquisition signal error estimator 有权
标题翻译：采集信号误差估计器
公开(公告)号：US06853509B2
公开(公告)日：2005-02-08
申请号：US10322243
申请日：2002-12-17
申请人： Jonathan Ashley , Stephen J. Franck , Razmik Karabed
发明人： Jonathan Ashley , Stephen J. Franck , Razmik Karabed
IPC分类号： G11B5/09 , G11B20/10 , G11B20/22
CPC分类号： G11B20/10037 , G11B5/09 , G11B20/10009 , G11B20/10055 , G11B20/22
摘要： A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample value without comparing the received sample value to the potential sample values. According to one embodiment, the nearest ideal sample value is selected based on the received sample value and values of three consecutive samples. According to another embodiment, the nearest ideal sample value is selected based on the received sample value and a value of an immediately preceding sample. According yet to another embodiment, the nearest ideal sample value is selected based on the received sample value and a value of a previous sample. The acquisition signal error estimator maybe used in conjunction with gain, DC offset, or magneto-resistive asymmetry control loops in a sampled amplitude read channel.
摘要翻译：提供了一种用于采集信号误差估计的系统和方法，其使用该序列的一个或多个过去值来确定最接近的理想采样值，而不将接收到的采样值与潜在采样值相比较。根据一个实施例，基于接收到的采样值和三个连续样本的值来选择最接近的理想采样值。根据另一个实施例，基于所接收的采样值和紧接在前的样本的值来选择最接近的理想采样值。根据另一个实施例，基于所接收的采样值和先前样本的值来选择最接近的理想采样值。采集信号误差估计器可以与采样幅度读通道中的增益，直流偏移或磁阻不对称控制环路结合使用。

52. 发明授权

US06774825B2 Modulation coding based on an ECC interleave structure 失效
标题翻译：基于ECC交错结构的调制编码
公开(公告)号：US06774825B2
公开(公告)日：2004-08-10
申请号：US10253909
申请日：2002-09-25
申请人： William G. Bliss , Andrei Vityaev , Razmik Karabed , Ali Najafi , Jonathan Ashley
发明人： William G. Bliss , Andrei Vityaev , Razmik Karabed , Ali Najafi , Jonathan Ashley
IPC分类号： H03M700
CPC分类号： H03M13/27 , G11B20/1426 , G11B20/1833 , G11B20/1866 , H03M5/145
摘要： A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks sorted into interleaves. A second encoder encodes a subset of the input blocks to produce output blocks, where the first encoder permutates a remainder of the input blocks and the output blocks to produce a codeword.
摘要翻译：基于ECC交错结构来调制编码的系统和方法包括编码包括被排序成交织的输入块的位的输入流的第一编码器。第二编码器编码输入块的子集以产生输出块，其中第一编码器排列剩余的输入块和输出块以产生码字。

53. 发明授权

US06594094B2 Read/write channel 有权
标题翻译：读/写通道
公开(公告)号：US06594094B2
公开(公告)日：2003-07-15
申请号：US10025001
申请日：2001-12-18
申请人： James W. Rae , William Bliss , Jonathan Ashley , Razmik Karabed , Stephen J. Franck , Fritz Mistlberger , Matthias Driller , Heinrich Stockmanns , Dominik Margraf
发明人： James W. Rae , William Bliss , Jonathan Ashley , Razmik Karabed , Stephen J. Franck , Fritz Mistlberger , Matthias Driller , Heinrich Stockmanns , Dominik Margraf
IPC分类号： G11B502
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B5/59688 , G11B5/6076 , G11B20/10009 , G11B20/10037
摘要： An improved sampled amplitude read/write channel is provided. The system is an integrated Generalized Partial Response Maximum Likelihood (GPRML) read channel incorporating Read, Write, and Servo modes of operation. One implementation includes a 32/34 rate parity code and matched Viterbi detector, a 32 state Viterbi detector optimal parity processor, robust frame synchronization, self-adaptive equalization, thermal asperity detection and compensation, adaptive magneto-resistive asymmetry compensation, low latency interpolated timing recovery and programmable write precompensation.
摘要翻译：提供了一种改进的采样幅度读/写通道。该系统是集成了读，写和伺服操作模式的集成广义部分响应最大似然（GPRML）读通道。一个实现包括32/34速率奇偶校验码和匹配维特比检测器，32状态维特比检测器最佳奇偶校验处理器，鲁棒帧同步，自适应均衡，热粗糙度检测和补偿，自适应磁阻不对称补偿，低延迟内插时序恢复和可编程预写。

54. 发明授权

US06549354B1 Acquisition signal error estimator 有权
公开(公告)号：US06549354B1
公开(公告)日：2003-04-15
申请号：US09653235
申请日：2000-08-31
申请人： Jonathan Ashley , Stephen J. Franck , Razmik Karabed
发明人： Jonathan Ashley , Stephen J. Franck , Razmik Karabed
IPC分类号： G11B509
CPC分类号： G11B20/10037 , G11B5/09 , G11B20/10009 , G11B20/10055 , G11B20/22
摘要： A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample value. According to one embodiment, four consecutive samples are used. According to another embodiment, two samples are used. The acquisition signal error estimator maybe used in conjunction with gain, DC offset, or magneto-resistive asymmetry control loops in a sampled amplitude read channel.

55. 发明授权

US06084535A System and method for generating many ones codes with hamming distance after precoding 失效
标题翻译：用于在预编码后产生汉明距离的多个代码的系统和方法
公开(公告)号：US06084535A
公开(公告)日：2000-07-04
申请号：US791687
申请日：1997-01-30
申请人： Razmik Karabed , Nersi Nazari , Andrew Popplewell , Isaiah A. Carew
发明人： Razmik Karabed , Nersi Nazari , Andrew Popplewell , Isaiah A. Carew
IPC分类号： G11B20/10 , G11B20/14 , H03M13/31 , H03M5/00
CPC分类号： G11B20/1426 , G11B20/10009 , H03M13/31
摘要： A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-( . . . 010-10 . . . ) error events and error events +/-( . . . 01000-10 . . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal. The encoder provides a "systematic" encoding scheme in which for many code strings the encoded bits are the same as the input bits used to generate the encoded bits. This systematic approach of the present invention provides an encoder that is easy to implement because a majority of the bits directly "feed through" and non-trivial logic circuits are only needed to generate the control bits. The systematic encoding also dictates a decoder that is likewise easy to construct and can be implemented in a circuit that simply discards the control bit. The encoder preferably comprises a serial-to-parallel converter, a code generator, and a parallel-to-serial converter. The code generator produces a rate 16/18 or 16/17 code. The present invention also includes a method that is directed to encoding bit strings and comprises the steps of: 1) converting the input strings to input bits, and 2) adding at least one bit to produce an encoded string with many ones and a Hamming distance greater than one after precoding.
摘要翻译：系统包括编码器，预编码器，PRML信道，检测器和解码器。输入信号由编码器接收。编码器通过添加一个或多个位来生成代码串，并将代码串输出到预编码器。编码器应用编码，使得通过预编码器之后的代码串具有大于1的汉明距离，以消除在PRML通道的输出处具有小距离的错误事件。本发明还提供了在预编码后具有2和0模数3的汉明距离的代码。当以交错方式在PRML通道上使用时，这些代码排除了+/-（... 010-10 ...）错误事件和错误事件+/-（... 01000-10 ...）。代码串还在PRML通道的输出处具有预定的最小数目，以帮助从输入信号导出时钟。编码器提供了一种“系统”编码方案，其中对于许多代码串，编码比特与用于生成编码比特的输入比特相同。本发明的这种系统方法提供了一种易于实现的编码器，因为大多数比特直接“馈送”和非平凡逻辑电路仅需要生成控制比特。系统编码还指示同样易于构造并且可以在简单地丢弃控制位的电路中实现的解码器。编码器优选地包括串行到并行转换器，代码生成器和并行到串行转换器。代码生成器生成16/18或16/17的代码。本发明还包括一种针对编码比特串的方法，包括以下步骤：1）将输入串转换成输入比特，以及2）添加至少一个比特以产生具有多个比特的编码串和汉明距离大于一个预编码后。

56. 发明授权

US5809081A System and method for encoding data such that after precoding the data has a pre-selected parity structure 失效
标题翻译：用于对数据进行编码的系统和方法，使得在预编码之后，数据具有预先选择的奇偶校验结构
公开(公告)号：US5809081A
公开(公告)日：1998-09-15
申请号：US650700
申请日：1996-05-20
申请人： Razmik Karabed , Nersi Nazari
发明人： Razmik Karabed , Nersi Nazari
IPC分类号： H03M13/47 , H04L1/00 , H04L25/497 , H04L5/12 , H04L23/02
CPC分类号： H04L1/0059 , H03M13/47 , H04L25/497
摘要： A system comprises an encoder, a precoder, a PR channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies such encoding such that the code string after being modified by the precoder has a pre-selected parity structure. The encoder provides a systematic encoding scheme in which many of the encoded bits are the same as the input bits used to generate the encoded bits. This systematic approach of the present invention provides an encoder that is easy to implement because a majority of the bits are directly "feed through" and non-trivial logic circuits are only needed to generate the control bits. The systematic encoding also dictates a decoder that is likewise easy to construct and can be implemented in a circuit that simply discards the control bit. The encoder preferably comprises a serial-to-parallel converter, a code generator and a parallel-to-serial converter. The code generator produces one of three trellis codes such as a rate 8/9, 8/10 or 9/11 code. The present invention also includes a method that is directed to encoding bit strings and comprises the steps of: 1) converting the input string to input bits, and 2) adding at least one bit to produce a pre-selected parity structure after precoding.
摘要翻译：系统包括编码器，预编码器，PR信道，检测器和解码器。输入信号由编码器接收。编码器通过添加一个或多个位来生成代码串，并将代码串输出到预编码器。编码器应用这样的编码，使得由预编码器修改之后的代码串具有预先选择的奇偶校验结构。编码器提供了一种系统编码方案，其中许多编码比特与用于生成编码比特的输入比特相同。本发明的这种系统方法提供了一种易于实现的编码器，因为大多数位直接“馈送”，并且只需要非平凡的逻辑电路来产生控制位。系统编码还指示同样易于构造并且可以在简单地丢弃控制位的电路中实现的解码器。编码器优选地包括串行到并行转换器，代码发生器和并行到串行转换器。代码生成器生成三种格式代码之一，例如速率为8/9,8/10或9/11代码。本发明还包括针对编码比特串的方法，包括以下步骤：1）将输入串转换成输入比特，以及2）在预编码之后添加至少一个比特以产生预先选择的奇偶校验结构。

57. 发明授权

US5537424A Matched spectral null codes with partitioned systolic trellis structures 失效
标题翻译：具有分割收缩网格结构的匹配的谱空代码
公开(公告)号：US5537424A
公开(公告)日：1996-07-16
申请号：US289811
申请日：1994-08-12
申请人： Razmik Karabed , James W. Rae , Paul H. Siegel , Hemant K. Thapar
发明人： Razmik Karabed , James W. Rae , Paul H. Siegel , Hemant K. Thapar
IPC分类号： H03M13/31 , H03M13/41 , H04L25/497 , H03M13/12
CPC分类号： H03M13/6343 , H03M13/31 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/4169 , H03M13/6502 , H04L25/497
摘要： Apparatus and method for transmitting spectral null sequences of a spectrally-constrained code over a partial response channel. A Viterbi detector receives the sequences from the channel and has a time-varying detector trellis structure derived from a running-digital-sum (RDS) trellis structure that requires each one of a set of quasicatastrophic sequences to be generated only from a trellis state corresponding to a respective preselected unique RDS value.
摘要翻译：用于在部分响应信道上发送频谱约束码的频谱零序列的装置和方法。维特比检测器从信道接收序列，并且具有从运行数字和（RDS）网格结构导出的时变检测器网格结构，其需要仅从对应的网格状态产生一组准基因阵列序列中的每一个到相应的预选的唯一RDS值。

58. 发明授权

US4888775A Trellis codes for partial response channels 失效
标题翻译：网格代码部分响应通道
公开(公告)号：US4888775A
公开(公告)日：1989-12-19
申请号：US169919
申请日：1988-03-18
申请人： Razmik Karabed , Paul H. Siegel
发明人： Razmik Karabed , Paul H. Siegel
IPC分类号： G11B20/10 , H03M13/23 , H04L25/08 , H04L25/49 , H04L25/497
CPC分类号： H04L25/4908 , H04L25/4915 , H04L25/497
摘要： An improved method is described for coding input strings to improve reliability of partial response channels. This method comprises encoding an input string into an intermediate string using a binary convolutional code, and encoding the intermediate string using a nonlinear inner code that repeats and inverts selected bits of the intermediate string. The inner code has a coding rate of less than one. As specifically illustrated, this method provides coding gains for partial response channels of at least 4.8 dB.

59. 发明授权

US10654422B2 View friendly monitor systems 有权
公开(公告)号：US10654422B2
公开(公告)日：2020-05-19
申请号：US15854558
申请日：2017-12-26
申请人： Razmik Karabed
发明人： Razmik Karabed
IPC分类号： B60R11/04 , B60R11/02 , G06K9/00 , G06K9/32 , B60R1/00
摘要： A view friendly monitor system provides a monitor and a sequence of views that are regions of interest. The monitor can display a region of the camera view; the system is configured such that the displayed region of the camera view is a region of interest to the user. The displayed portion of the camera view changes to match the changing interests of the user. For example, a user that is interested to see a view in a direction beyond a certain edge of the monitor would move her head generally in an opposite direction. To see farther outside the edge, she needs to move her head farther in the opposite direction. In response to her head movement, the view friendly monitor system would change the region of interest based on the direction and the length of her head movement and display the new region of interest on the monitor.

60. 发明授权

US09419651B2 Non-polynomial processing unit for soft-decision error correction coding 有权
标题翻译：用于软判决纠错编码的非多项式处理单元
公开(公告)号：US09419651B2
公开(公告)日：2016-08-16
申请号：US12651386
申请日：2009-12-31
申请人： Razmik Karabed , Hakan C. Ozdemir , Vincent Brendan Ashe , Richard Barndt
发明人： Razmik Karabed , Hakan C. Ozdemir , Vincent Brendan Ashe , Richard Barndt
IPC分类号： H03M13/15 , G11B20/18 , H03M13/37 , H03M13/45
CPC分类号： H03M13/1515 , G11B20/1833 , G11B2020/1836 , G11B2220/2516 , H03M13/373 , H03M13/451
摘要： A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method.
摘要翻译：一种用于使用软判决数据来校正ECC块中的错误的系统和方法。在一个实施例中，软判决ECC解码方法使用指示数据可靠位读出时的“软”数据。这种方法可以使用更新模块来接收和操纵软判决数据，并且基于可靠性因素的排序迭代地改变比特或比特组。然后，计算器模块可以确定在每次迭代之后仍然存在的错误的总数。仅确定总错误数量而不是实际位置的计算密集程度远低于计算密集度，因此可以快速分析潜在的翻转比特组合的许多组合，以确定是否有任何组合可能会减少足够数量的错误，以便由常规的硬判决ECC解码方法。

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