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1. 发明授权

US08892966B2 Methods and apparatus for soft data generation for memory devices using decoder performance feedback 有权
标题翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置
公开(公告)号：US08892966B2
公开(公告)日：2014-11-18
申请号：US13063899
申请日：2009-09-30
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Clifton Williamson , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Clifton Williamson , Johnson Yen
IPC分类号： G06F11/00 , G11C29/00 , G11C7/04 , G11C16/04 , G11C16/26 , G11C7/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/1032 , G06F2212/2022 , G11C7/02 , G11C7/04 , G11C11/16 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5634
摘要： Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.
摘要翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置。通过从解码器获得性能反馈，在存储器件中产生至少一个软数据值; 基于性能反馈获得误差统计; 以及基于所获得的误差统计量生成所述至少一个软数据值。性能反馈包括解码比特中的一个或多个，基于由解码器解码的数据的多个错误比特和多个不满足的奇偶校验。

2. 发明授权

US08429500B2 Methods and apparatus for computing a probability value of a received value in communication or storage systems 有权
标题翻译：用于计算通信或存储系统中的接收值的概率值的方法和装置
公开(公告)号：US08429500B2
公开(公告)日：2013-04-23
申请号：US12751960
申请日：2010-03-31
申请人： Erich F. Haratsch , Nenad Miladinovic , Andrei Vityaev
发明人： Erich F. Haratsch , Nenad Miladinovic , Andrei Vityaev
IPC分类号： G11C29/00
CPC分类号： H03M13/612 , H03M13/1102 , H03M13/2957 , H03M13/3905 , H03M13/41 , H03M13/4138 , H04L1/005
摘要： Methods and apparatus are provided for computing a probability value of a received value in communication or storage systems. A probability value for a received value in a communication system or a memory device is computed by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the probability value using the set of parameters associated with the identified segment. A probability value for a received value in a communication system or a memory device can also be computed by calculating the probability value for the received value using a first distribution, wherein the first distribution is predefined and wherein a mapped version of the first distribution approximates a distribution of the received values and wherein the calculating step is implemented by a processor, a controller, a read channel, a signal processing unit or a decoder.
摘要翻译：提供了用于计算通信或存储系统中的接收值的概率值的方法和装置。通过获得至少一个接收值来计算通信系统或存储设备中的接收值的概率值; 识别对应于所接收的值的功能的片段，其中所述功能在多个片段上被定义，其中所述片段中的每个片段具有相关联的参数组; 以及使用与所识别的段相关联的参数集来计算概率值。也可以通过使用第一分布计算接收值的概率值来计算通信系统或存储器件中的接收值的概率值，其中第一分布是预定义的，并且其中第一分布的映射版本近似于分配接收值，其中计算步骤由处理器，控制器，读通道，信号处理单元或解码器来实现。

3. 发明申请

US20110216586A1 Methods And Apparatus For Intercell Interference Mitigation Using Modulation Coding 有权
标题翻译：使用调制编码的小区间干扰减轻的方法和装置
公开(公告)号：US20110216586A1
公开(公告)日：2011-09-08
申请号：US13001310
申请日：2009-06-30
申请人： Nils Graef , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Andrei Vityaev , Johnson Yen
发明人： Nils Graef , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Andrei Vityaev , Johnson Yen
IPC分类号： G11C16/12 , G11C16/04 , G11C16/26
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.
摘要翻译：提供了使用调制编码的小区间干扰减轻的方法和装置。在闪速存储器的编程期间，执行调制编码，其选择用于编程闪速存储器的一个或多个级别，使得闪存中的减少数量的单元被编程为具有违反一个或多个预定标准的值。在读取闪速存储器期间，执行调制解码，其向闪存中的单元分配一个或多个电平，使得闪存中的单元数目减少，其值违反一个或多个预定准则。预定义的标准可以例如基于由编程的小区引起的干扰量的一个或多个; 编程单元的电压偏移：由编程单元存储的电压; 通过编程单元的电流变化量; 以及通过编程单元的电流量。

4. 发明授权

US07260167B1 Method and apparatus for synchronization of a bit stream for long latency date detection 有权
标题翻译：用于长时间延迟日期检测的位流同步的方法和装置
公开(公告)号：US07260167B1
公开(公告)日：2007-08-21
申请号：US10768907
申请日：2004-02-02
申请人： Pantas Sutardja , Andrei Vityaev
发明人： Pantas Sutardja , Andrei Vityaev
IPC分类号： H04L7/06
CPC分类号： H04L7/042 , G11B20/10009 , G11B20/1217 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1287 , G11B2020/1476
摘要： A method is for decoding a bit stream from a waveform representing the bit stream, having a first synchronization mark, data, and a second synchronization mark. Digitized samples are decoded to form a reconstructed bit stream. The reconstructed bit stream is then stored. At least one of the first synchronization mark and the second synchronization mark are then extracted from the reconstructed bit stream. Finally, the data are extracted from the reconstructed bit stream using an iterative decoding process, in accordance with at least one of the first synchronization mark and the second synchronization mark. As such, loss of the data between the first synchronization mark and the second synchronization mark, if there is a problem with the first synchronization mark, is avoided.
摘要翻译：一种方法是从表示具有第一同步标记，数据和第二同步标记的比特流的波形对比特流进行解码。数字样本被解码以形成重构比特流。然后存储重建的比特流。然后从重建的比特流中提取第一同步标记和第二同步标记中的至少一个。最后，根据第一同步标记和第二同步标记中的至少一个，使用迭代解码处理从重建的位流中提取数据。因此，避免了第一同步标记与第二同步标记之间的数据的丢失，如果存在第一同步标记的问题。

5. 发明授权

US09294132B1 Dual-stage data decoding for non-volatile memories 有权
标题翻译：用于非易失性存储器的双级数据解码
公开(公告)号：US09294132B1
公开(公告)日：2016-03-22
申请号：US13672047
申请日：2012-11-08
申请人： Borja Peleato-Inarrea , Andrei Vityaev , Nenad Miladinovic
发明人： Borja Peleato-Inarrea , Andrei Vityaev , Nenad Miladinovic
IPC分类号： H03M13/29 , G11B20/18 , H03M13/39 , G06F11/10 , H03M13/27
CPC分类号： H03M13/29 , G06F11/1048 , G06F11/1068 , G11B20/1833 , G11B2020/1846 , G11B2020/185 , H03M13/1108 , H03M13/1117 , H03M13/27 , H03M13/2948 , H03M13/3707 , H03M13/3927 , H03M13/6325
摘要： A method and system for decoding information read from a non-volatile memory uses a two stage decoding algorithm, where the first stage is a high-speed, low precision decoder and the second stage is a low-speed, high precision decoder. Most of the time only the first stage of the decoder is used, which lowers the average power consumption of the decoding process.
摘要翻译：用于解码从非易失性存储器读取的信息的方法和系统使用两级解码算法，其中第一级是高速，低精度解码器，第二级是低速，高精度解码器。大多数时候只使用解码器的第一级，这降低了解码过程的平均功耗。

6. 发明授权

US08634250B2 Methods and apparatus for programming multiple program values per signal level in flash memories 有权
标题翻译：闪存中每个信号电平编程多个程序值的方法和装置
公开(公告)号：US08634250B2
公开(公告)日：2014-01-21
申请号：US13001295
申请日：2009-07-21
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.
摘要翻译：提供了用于在闪速存储器中编程每个信号电平的多个程序值的方法和装置。具有多个编程值的闪速存储器件通过针对给定的信号电平对闪速存储器件进行编程来编程，其中编程步骤包括编程阶段和多个验证阶段。在另一个实施例中，编程具有多个编程值的闪速存储器件，并且编程步骤包括编程阶段和多个验证阶段，其中至少一个信号电平包括多个程序值。可以使用电压，电流和电阻中的一个或多个来表示信号电平或程序值（或两者）。

7. 发明授权

US08526230B2 Methods and apparatus for write-side intercell interference mitigation in flash memories 失效
标题翻译： Flash存储器中写入侧小区间干扰减轻的方法和装置
公开(公告)号：US08526230B2
公开(公告)日：2013-09-03
申请号：US13001286
申请日：2009-06-30
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Johnson Yen
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.
摘要翻译：提供了用于闪存中的写侧小区间干扰减轻的方法和装置。通过获得写入到闪速存储器中的至少一个目标单元的程序数据来写入闪速存储器件; 为至少一个侵略者单元获得待编程的比目标小区晚的一个或多个程序数据位;并且通过产生预补偿的程序值来预补偿目标小区的小区间干扰。侵略者细胞包括与靶细胞相邻的一个或多个细胞，例如与靶细胞相同的字线中的相邻细胞和/或与靶细胞的上或下相邻字线中的细胞。目标单元的预补偿程序值可选地提供给闪存。

8. 发明授权

US08429489B2 Data retrieval from a storage device using a combined error correction and detection approach 失效
标题翻译：使用组合的纠错和检测方法从存储设备进行数据检索
公开(公告)号：US08429489B2
公开(公告)日：2013-04-23
申请号：US12200528
申请日：2008-08-28
申请人： Andrei Vityaev
发明人： Andrei Vityaev
IPC分类号： G11C29/00 , H03M13/29
CPC分类号： G11B20/1833 , H03M13/1515
摘要： One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.
摘要翻译：提出了一种或多种有效地检索存储在存储设备的介质中的数据的方法和系统。一种或多种方法和系统通过使用多级解码过程校正和检测错误来实现。在一个实施例中，存储设备包括磁性硬盘驱动器。在一个实施例中，系统和方法应用允许在多个连续解码级或处理级上执行错误校正和检测的编码/解码技术。使用该系统和方法增加了可以在编码码字中校正的符号错误的最大数目，从而提供了数据恢复的改进。

9. 发明授权

US07822138B2 Calculating apparatus and method for use in a maximum likelihood detector and/or decoder 有权
标题翻译：用于最大似然检测器和/或解码器的计算装置和方法
公开(公告)号：US07822138B2
公开(公告)日：2010-10-26
申请号：US10867179
申请日：2004-06-14
申请人： Oleg Zaboronski , Nicholas Atkinson , Robert Charles Jackson , Theo Drane , Andrei Vityaev
发明人： Oleg Zaboronski , Nicholas Atkinson , Robert Charles Jackson , Theo Drane , Andrei Vityaev
IPC分类号： H04L5/12 , H03M13/03
CPC分类号： H03M13/395 , H03M13/4107 , H03M13/4138
摘要： A calculator for use in a maximum likelihood detector, including: a receiver for receiving convolution encoded data which may include noise; first calculator for calculating a first component of a first path metric difference between two possible sequences of states corresponding to the convolution encoded data, the two sequences each having a length equal to a constraint length of the convolution encoded data, and the two sequences starting at a same state and ending at a same state, adapted to calculate the first component using the convolution-encoded data and using convolution encoding parameters of the convolution-encoded data, wherein the first component is independent of the two sequences; and second calculator for calculating a second component of the first path metric difference using the two sequences, wherein the second component is independent of the convolution encoded data; and using the first and second components to obtain the first path metric difference.
摘要翻译：一种用于最大似然检测器的计算器，包括：接收器，用于接收可包括噪声的卷积编码数据; 第一计算器，用于计算与卷积编码数据相对应的两个可能状态序列之间的第一路径度量差的第一分量，每个具有等于卷积编码数据的约束长度的长度的两个序列，以及从相同的状态并且以相同的状态结束，适于使用卷积编码的数据计算第一分量并使用卷积编码数据的卷积编码参数，其中第一分量独立于两个序列; 以及第二计算器，用于使用所述两个序列来计算所述第一路径量度差的第二分量，其中所述第二分量与所述卷积编码数据无关; 以及使用第一和第二分量来获得第一路径度量差。

10. 发明授权

US07426676B2 Data retrieval from a storage device using a combined error correction and detection approach 有权
标题翻译：使用组合的纠错和检测方法从存储设备进行数据检索
公开(公告)号：US07426676B2
公开(公告)日：2008-09-16
申请号：US10757260
申请日：2004-01-14
申请人： Andrei Vityaev
发明人： Andrei Vityaev
IPC分类号： H03M13/15
CPC分类号： G11B20/1833 , H03M13/1515
摘要： One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.
摘要翻译：提出了一种或多种有效地检索存储在存储设备的介质中的数据的方法和系统。一种或多种方法和系统通过使用多级解码过程校正和检测错误来实现。在一个实施例中，存储设备包括磁性硬盘驱动器。在一个实施例中，系统和方法应用允许在多个连续解码级或处理级上执行错误校正和检测的编码/解码技术。使用该系统和方法增加了可以在编码码字中校正的符号错误的最大数目，从而提供了数据恢复的改进。

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