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51. 发明授权

US6133932A Method and apparatus for adjusting a line synchronization signal in response to photoreceptor motion 失效
标题翻译：响应感光体运动调整线同步信号的方法和装置
公开(公告)号：US6133932A
公开(公告)日：2000-10-17
申请号：US358490
申请日：1994-12-19
申请人： Douglas E. Webb , Charles J. Mirabella, Jr. , Robert Mara , Charles E. Smith
发明人： Douglas E. Webb , Charles J. Mirabella, Jr. , Robert Mara , Charles E. Smith
IPC分类号： B41J2/525 , B41J2/44 , G03G15/01 , G03G21/00 , G03G21/14 , H03L7/16 , H04N1/047 , H04N1/113 , H04N1/12 , H04N1/50 , H04N1/60 , B41J2/06
CPC分类号： G03G15/0152 , G03G15/0163 , H04N1/0473 , H04N1/506 , G03G2215/0158 , G03G2215/017 , H04N1/1135 , H04N1/12 , H04N2201/0471 , H04N2201/04756 , H04N2201/04786
摘要： The present invention is a method and apparatus for modifying line synchronization signals that drive at least one secondary image exposure device in a multicolor printing or reprographic system. The ability to alter the line synchronization signals enables the accurate registration of a multiple color images on a photoconductor in response to detected photoreceptor motion. More specifically, the first color image is deposited on the photoreceptor using a servomotor control system to control photoreceptor velocity as a function of the desired raster line spacing, or the frequency at which the individual raster lines are deposited. All subsequently added colors in the single-pass printing system are added under the control of phase-locked loops, wherein the line synchronization pulses are produced as a function of the photoreceptor speed, to correct for variations from the nominal photoreceptor velocity.
摘要翻译：本发明是用于修改在多色打印或复制系统中驱动至少一个次要图像曝光装置的线同步信号的方法和装置。改变线同步信号的能力使得能够响应于检测到的感光器运动而在感光体上精确配准多个彩色图像。更具体地，使用伺服电动机控制系统将第一彩色图像沉积在感光体上，以根据期望的光栅线间隔或者各个光栅线被沉积的频率来控制光感受器速度。在单通道打印系统中所有随后添加的颜色在锁相环的控制下被添加，其中线同步脉冲作为光感受器速度的函数产生，以校正来自标称感光体速度的变化。

52. 发明授权

US6091303A Method and apparatus for reducing oscillator noise by noise-feedforward 有权
标题翻译：通过噪声前馈降低振荡器噪声的方法和装置
公开(公告)号：US6091303A
公开(公告)日：2000-07-18
申请号：US286857
申请日：1999-04-06
申请人： Paul W. Dent
发明人： Paul W. Dent
IPC分类号： H03L7/22 , H03C3/09 , H03C5/00 , H03L7/087 , H03L7/23 , H04B1/04 , H04L27/20 , H03C1/00 , H03C3/00 , H03L7/07 , H03L7/16 , H04L27/00
CPC分类号： H03C3/0966 , H03C5/00 , H03L7/0805 , H03L7/23 , H04L27/2014
摘要： A circuit for reducing phase noise in a transmitted radio signal includes a first phase-locked loop circuit including a first controlled oscillator generating a first output signal at a first desired frequency, and a first phase comparator developing a first phase error signal to control the first controlled oscillator, the first error signal representative of phase differences between the first output signal and the first desired frequency. A second phase-locked loop circuit includes a second controlled oscillator generating a second output signal at a desired frequency of transmission related to the first desired frequency, and a second phase comparator developing a second phase error signal representative of phase differences between the first output signal and the desired frequency of transmission. A summer combines the first and second error signals to control the second controlled oscillator to thereby reduce, or cancel, phase noise generated by the first controlled oscillator in the second output signal transmitted as a radio signal at the desired frequency of transmission.
摘要翻译：用于减少所发送的无线电信号中的相位噪声的电路包括第一锁相环电路，其包括产生第一期望频率的第一输出信号的第一受控振荡器，和形成第一相位误差信号以控制第一相位误差信号的第一相位比较器控制振荡器，第一误差信号表示第一输出信号和第一期望频率之间的相位差。第二锁相环电路包括第二受控振荡器，以与所述第一期望频率相关的期望的传输频率产生第二输出信号，以及第二相位比较器，产生表示所述第一输出信号之间的相位差的第二相位误差信号和所需的传输频率。夏天组合第一和第二误差信号以控制第二受控振荡器，从而减少或消除由作为无线电信号以期望的传输频率发送的第二输出信号中的第一受控振荡器产生的相位噪声。

53. 发明授权

US6087864A Digital frequency multiplier circuit including delay circuit 失效
标题翻译：数字倍频电路包括延时电路
公开(公告)号：US6087864A
公开(公告)日：2000-07-11
申请号：US967106
申请日：1997-11-10
申请人： Akira Aoki
发明人： Akira Aoki
IPC分类号： H03B19/00 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/0805 , H03K5/00006 , H03K5/133 , H03L7/0814 , H03L7/16 , H03K2005/00026
摘要： A frequency multiplier circuit device having a delay circuit including a plurality of delay elements, and a selector circuit for selecting the number of delay elements for every output stage of the delay circuit. A reference input signal and an output from the selector circuit for determining the period of the reference input signal are input to a phase comparator. The selector circuit is controlled on the basis of an output from the phase comparator to select the number of delay elements of the delay circuit, so as to generate a signal for multiplying a frequency by N, so that the signal is supplied to an exclusive NOR circuit to output a signal having a frequency an N-number of times that of the reference input signal.
摘要翻译：一种具有包括多个延迟元件的延迟电路的倍频电路装置，以及选择电路，用于选择延迟电路的每个输出级的延迟元件的数量。参考输入信号和来自选择器电路的用于确定参考输入信号的周期的输出被输入到相位比较器。基于相位比较器的输出来控制选择器电路，以选择延迟电路的延迟元件的数量，以便产生用于将频率乘以N的信号，使得信号被提供给异或电路以输出具有基准输入信号的N倍频率的信号。

54. 发明授权

US5889436A Phase locked loop fractional pulse swallowing frequency synthesizer 失效
$Phase locked loop fractional pulse swallowing frequency synthesizer$
标题翻译：锁相环分数脉冲吞咽频率合成器
公开(公告)号：US5889436A
公开(公告)日：1999-03-30
申请号：US742331
申请日：1996-11-01
申请人： Pak-Ho Yeung , Kern Wai Wong , Laurence D. Lewicki
发明人： Pak-Ho Yeung , Kern Wai Wong , Laurence D. Lewicki
IPC分类号： H03L7/081 , H03L7/099 , H03L7/16 , H03L7/23
CPC分类号： H03L7/0996 , H03L7/081 , H03L7/16 , H03L7/23
摘要： A phase-locked loop (PLL) frequency synthesizer is described which incorporates a fractional pulse swallowing circuit. The fractional pulse swallowing circuit does not add or delete pulses but extends or shortens pulses by a fractional amount. This avoids large phase errors generated by a phase detector in the PLL. In the preferred embodiment, the PLL uses a voltage controlled oscillator (VCO) formed of a ring oscillator. The outputs of the stages of the ring oscillator are applied to input terminals of a multiplexer. The multiplexer is controlled at certain times to output a different tapped signal from the ring oscillator to effectively adjust the phase of the signal output from the multiplexer. By so controlling the multiplexer, fractional pulses are subtracted or added at intervals to either increase or decrease the average frequency of the signal output from the multiplexer. The output of the VCO is fed back to the input of a phase detector along with a reference frequency. Alternatively, the output of the pulse swallower, and not the VCO, provides the feedback signal for the phase detector.
摘要翻译：描述了一种包含分数脉冲吞咽电路的锁相环（PLL）频率合成器。分数脉冲吞咽电路不会增加或删除脉冲，而是延伸或缩短脉冲数量。这避免了由PLL中的相位检测器产生的大的相位误差。在优选实施例中，PLL使用由环形振荡器形成的压控振荡器（VCO）。环形振荡器的级的输出被施加到多路复用器的输入端。多路复用器在某些时间被控制，以从环形振荡器输出不同的抽头信号，以有效地调整从多路复用器输出的信号的相位。通过这样控制多路复用器，可以间隔地减小或添加分数脉冲，以增加或减少从多路复用器输出的信号的平均频率。 VCO的输出与参考频率一起被反馈到相位检测器的输入端。或者，脉冲吞咽器（而不是VCO）的输出为相位检测器提供反馈信号。

55. 发明授权

US5847615A Frequency synthesizer operating according to the principle of fractional frequency synthesis 失效
$Frequency synthesizer operating according to the principle of fractional frequency synthesis$
标题翻译：频率合成器根据分数频率合成的原理工作
公开(公告)号：US5847615A
公开(公告)日：1998-12-08
申请号：US948587
申请日：1997-10-10
申请人： Alexander Roth
发明人： Alexander Roth
IPC分类号： H03L7/16 , H03L7/185 , H03L7/197 , H03L7/06 , H03L7/18
CPC分类号： H03L7/1976 , H03L7/185 , H03L2207/12
摘要： A frequency synthesizer operating according to fractional frequency synthesis, has a phase-controlled oscillator, a phase detector that controls this oscillator, a loop filter arranged in a control line between the phase detector and the oscillator, a reference frequency source and a frequency divider arranged between this reference frequency source and one input of the phase detector, which frequency divider can be adjusted to whole-number division ratios. The frequency synthesizer also has an adjustment device that operates with multiple integration, by which the whole-number division ratio of the frequency divider is controlled such that a fractional division ratio corresponding to a desired fractional rational division ratio is simulated. The other input of the phase detector is connected with the output of the oscillator via a mixer, wherein a difference is formed of the output frequency of the oscillator and the reference frequency of the reference frequency source.
摘要翻译：根据分数频率合成器操作的频率合成器具有相位控制振荡器，控制该振荡器的相位检测器，布置在相位检测器和振荡器之间的控制线中的环路滤波器，基准频率源和分频器在该参考频率源和相位检测器的一个输入之间，哪个分频器可以调整为全数分频比。频率合成器还具有以多重积分运行的调整装置，通过该调整装置控制分频器的全数分频比，使得对应于期望的分数有理分频比的分数比率被模拟。相位检测器的另一输入端通过混频器与振荡器的输出端相连，其中由振荡器的输出频率和参考频率源的参考频率形成差值。

56. 发明授权

US5838178A Phase-locked loop and resulting frequency multiplier 失效
标题翻译：锁相环和产生的倍频器
公开(公告)号：US5838178A
公开(公告)日：1998-11-17
申请号：US921334
申请日：1997-08-29
申请人： Roland Marbot
发明人： Roland Marbot
IPC分类号： H03B19/00 , H03B19/14 , H03K5/00 , H03L7/081 , H03L7/089 , H03L7/16
CPC分类号： H03B19/00 , H03B19/14 , H03K5/00006 , H03L7/0814 , H03L7/089 , H03L7/16
摘要： The frequency multiplier 10 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.
摘要翻译：倍频器10由包括相位比较器11的锁相环实现，该相位比较器11用于指令多个延迟元件130至137，延迟元件130至137将连续的相移信号CL0-CL7提供给由“独占或”门构成的逻辑加法器16。

57. 发明授权

US5831481A Phase lock loop circuit having a broad loop band and small step frequency 失效
标题翻译：锁相环电路具有宽环带和小步进频率
公开(公告)号：US5831481A
公开(公告)日：1998-11-03
申请号：US805501
申请日：1997-02-26
申请人： Toshiyuki Oga
发明人： Toshiyuki Oga
IPC分类号： H03B28/00 , G06F7/60 , H03L7/16 , H03L7/185
CPC分类号： H03L7/185 , G06F7/605 , H03L2207/12
摘要： A phase lock loop circuit includes an oscillator, a digital mixer, a comparator, a loop amplifier, and a low-pass filter. The oscillator has an oscillation frequency controlled by a control voltage. The digital mixer is constituted by a digital element to output a difference frequency signal between an oscillation output from the oscillator and an input mixing signal. The comparator compares at least the phase of the difference frequency signal output from the digital mixer with that of a reference frequency signal, and outputs a difference signal. The loop amplifier and the low-pass filter generate the control voltage for the voltage controlled oscillator on the basis of the difference signal output from the comparator.
摘要翻译：锁相环电路包括振荡器，数字混频器，比较器，环路放大器和低通滤波器。振荡器具有由控制电压控制的振荡频率。数字混频器由数字元件构成，以在振荡器的振荡输出和输入混合信号之间输出差分频率信号。比较器至少将从数字混频器输出的差频信号的相位与参考频率信号的相位相比较，并输出差分信号。环路放大器和低通滤波器根据从比较器输出的差分信号产生压控振荡器的控制电压。

58. 发明授权

US5825254A Frequency converter for outputting a stable frequency by feedback via a phase locked loop 失效
标题翻译：变频器，用于通过锁相环反馈输出稳定的频率
公开(公告)号：US5825254A
公开(公告)日：1998-10-20
申请号：US816947
申请日：1997-03-19
申请人： Sang-Bok Lee
发明人： Sang-Bok Lee
IPC分类号： H03L7/16 , H03L7/23 , H03L7/00
CPC分类号： H03L7/16 , H03L7/23 , H03L2207/12
摘要： A frequency converter capable of providing a highly stable frequency by frequency feedback using a phase locked loop circuit. The frequency converter includes a local oscillator; a frequency converter for mixing an output of the local oscillator and a feedback frequency therefrom to generate a mixed frequency; a first filter for filtering the mixed frequency; a phase comparator for generating a voltage signal corresponding to a phase difference in between an input frequency to the frequency convertor and the output frequency of the first filter; a second filter for converting the voltage signal of the phase comparator to a constant polarity voltage and eliminating any noise component of the converted voltage signal; and a voltage controlled oscillator receiving the output of the second filter as a control voltage so as to provide a stable output frequency by generating the feedback frequency responsive to the control voltage.
摘要翻译：一种能够使用锁相环电路通过频率反馈提供高度稳定的频率的变频器。变频器包括本地振荡器; 用于混合本地振荡器的输出和其反馈频率的频率转换器，以产生混频; 用于滤波混频的第一滤波器; 相位比较器，用于产生与频率转换器的输入频率和第一滤波器的输出频率之间的相位差相对应的电压信号; 第二滤波器，用于将相位比较器的电压信号转换为恒定极性电压，并消除转换的电压信号的任何噪声分量; 以及接收第二滤波器的输出作为控制电压的压控振荡器，以响应于控制电压产生反馈频率来提供稳定的输出频率。

59. 发明授权

US5801559A Clock generating circuit, PLL circuit, semiconductor device, and methods for designing and making the clock generating circuit 失效
标题翻译：时钟发生电路，PLL电路，半导体器件，以及用于设计和制造时钟发生电路的方法
公开(公告)号：US5801559A
公开(公告)日：1998-09-01
申请号：US588934
申请日：1996-01-19
申请人： Katsunori Sawai , Yukihiko Shimazu
发明人： Katsunori Sawai , Yukihiko Shimazu
IPC分类号： G06F1/10 , G11C11/407 , H03K3/02 , H03K5/00 , H03K5/135 , H03L7/081 , H03L7/087 , H03L7/16 , H03L7/18 , H03L7/00
CPC分类号： G06F1/10 , H03K5/135 , H03L7/0814 , H03L7/087 , H03L7/16
摘要： A clock generating circuit includes a plurality of delay lines connected in cascade, each delay line including two switching elements for letting in or shutting out a clock, and a delay element connected to each of the switching elements. A PLL circuit and a semiconductor device both include the clock generating circuit. The number K of the delay units in each of the delay lines of the clock generating circuit is calculated from: K>�{1/(2.multidot.N.multidot.F.sub.ref)}-(T.sub.mul)!/(T.sub.dmin)
摘要翻译：时钟发生电路包括串联连接的多个延迟线，每个延迟线包括两个用于允许或关闭时钟的开关元件，以及连接到每个开关元件的延迟元件。 PLL电路和半导体器件都包括时钟发生电路。时钟发生电路的每个延迟线中的延迟单元的数量K由下式计算：K> [{1 /（2xNxFref）} - （Tmul）] /（Tdmin）

60. 发明授权

US5786732A Phase locked loop circuitry including a multiple frequency output voltage controlled oscillator circuit 失效
标题翻译：锁相环电路包括多频输出压控振荡器电路
公开(公告)号：US5786732A
公开(公告)日：1998-07-28
申请号：US763479
申请日：1996-12-11
申请人： Edward T. Nielson
发明人： Edward T. Nielson
IPC分类号： H03L7/18 , G06F7/60 , H03K3/0231 , H03K3/03 , H03K5/00 , H03K5/15 , H03L7/08 , H03L7/099 , H03L7/16 , H03B5/24
CPC分类号： H03K3/0231 , G06F7/605 , H03K3/03 , H03K3/0322 , H03K5/00006 , H03L7/0995 , H03L7/0997 , H03L7/16 , H03L7/18 , H03L2207/10
摘要： A phase locked loop including a comparator, a VCO controller, and a VCO having a multi-stage oscillator portion and a combinational logic portion. The comparator is responsive to an input clock and a VCO comparison clock and is operative to produce a comparator output signal. The VCO controller is responsive to the comparator output signal and is operative to produce a VCO control signal. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of the VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency. A method for multiplying an input clock frequency includes the steps of applying an input clock to a delay chain, developing a plurality of phase-shifted clocks by tapping into the delay chain, and combining the plurality of phase-shifted clock in combinational logic to produce an output clock having a frequency that is a multiple of the input clock frequency.
摘要翻译：一种锁相环，包括比较器，VCO控制器和具有多级振荡器部分和组合逻辑部分的VCO。比较器响应于输入时钟和VCO比较时钟，并且可操作以产生比较器输出信号。 VCO控制器响应于比较器输出信号并且可操作地产生VCO控制信号。多级振荡器部分被配置为在VCO控制信号的控制下在稳态条件下以VCO时钟频率振荡，并且还可操作以在VCO时钟频率下产生多个时钟相位。组合逻辑部分响应于多个时钟相位中的至少一些，并且可操作以组合时钟相位以创建具有作为输入时钟频率的倍数的输出时钟频率的输出时钟。一种用于乘以输入时钟频率的方法包括以下步骤：将输入时钟施加到延迟链，通过点击延迟链来显影多个相移时钟，以及组合多个相移时钟在组合逻辑中产生具有作为输入时钟频率的倍数的频率的输出时钟。

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