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51. 发明授权

US09490967B1 Communication system and method 有权
标题翻译：通信系统及方法
公开(公告)号：US09490967B1
公开(公告)日：2016-11-08
申请号：US14978363
申请日：2015-12-22
申请人： Texas Instruments Incorporated
发明人： Robert Floyd Payne
IPC分类号： H04L5/20 , H04L7/027 , H04L25/02 , H04L1/00 , H04L7/00 , H04L25/14
CPC分类号： H04L25/0272 , G06F13/38 , H04L1/0045 , H04L7/0008 , H04L7/0066 , H04L25/4917
摘要： A communication system includes a receiver for decoding data having three states of −1, 0, and 1. The receiver includes a first input coupled to a first data line, a second input coupled to a second data line, and a third input coupled to a third data line. A first comparator is coupled to a first output, wherein the first comparator is for generating data signals in response to the sign of voltages on the first data line minus voltages on the second data line. A second comparator is coupled to a second output, wherein the second comparator is for generating clock signals in response to the sign of voltages on the third data line minus the average of voltages on the first and second data lines.
摘要翻译：通信系统包括用于解码具有三个状态-1,0和1的数据的接收器。接收机包括耦合到第一数据线的第一输入，耦合到第二数据线的第二输入和耦合到第二数据线的第三输入第三条数据线。第一比较器耦合到第一输出，其中第一比较器用于响应于第一数据线上的电压的符号减去第二数据线上的电压来产生数据信号。第二比较器耦合到第二输出，其中第二比较器用于响应于第三数据线上的电压的符号减去第一和第二数据线上的电压的平均来产生时钟信号。

52. 发明授权

US09490964B2 Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period 有权
标题翻译：符号转换时钟时钟和数据恢复，以在稳定的符号周期期间抑制由符号毛刺引起的多余时钟
公开(公告)号：US09490964B2
公开(公告)日：2016-11-08
申请号：US14555097
申请日：2014-11-26
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku
IPC分类号： H04L27/10 , H03D13/00 , H04L7/00 , H04L7/04 , H04L7/08 , G11C8/06 , G06F13/40 , H04L7/033 , H04L25/14 , H04L25/49
CPC分类号： H04L7/0087 , G06F13/4072 , G11C8/06 , H04L7/0037 , H04L7/0083 , H04L7/033 , H04L7/042 , H04L7/08 , H04L25/14 , H04L25/49
摘要： A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a first set-reset latch that provides a filtered version of the comparison signal, where the first set-reset latch is set by a first-occurring active transition of the comparison signal and is unaffected by further transitions of the comparison signal that occur during a predefined period of time, delay circuitry that receives the filtered version of the comparison signal and outputs a first pulse on a first clock signal, and a second set-reset latch configured to provide a second pulse on an output clock signal when the first pulse is present on the first clock signal and the comparison signal indicates that the level-latched instance of the input signal does not match the input signal.
摘要翻译：提供了一种方法和装置。该装置可以包括具有比较器的时钟恢复电路，该比较器提供指示输入信号是否匹配输入信号的电平锁存实例的比较信号，提供比较信号的滤波版本的第一设置复位锁存器，其中第一设置复位锁存器由比较信号的第一次有效转换设置，并且不受在预定时间段期间发生的比较信号的进一步转换的影响，接收比较信号的滤波版本的延迟电路和输出第一时钟信号上的第一脉冲和第二设置复位锁存器，其被配置为当第一时钟信号上存在第一脉冲时，在输出时钟信号上提供第二脉冲，并且比较信号指示电平锁存的实例输入信号与输入信号不匹配。

53. 发明申请

US20160323126A1 WIRELESS DEVICE AND DATA TRANSFER METHOD 审中-公开
标题翻译：无线设备和数据传输方法
公开(公告)号：US20160323126A1
公开(公告)日：2016-11-03
申请号：US15081920
申请日：2016-03-27
申请人： FUJITSU LIMITED
发明人： Noboru MASUDA , Junya MORITA , Kenji IWAI
IPC分类号： H04L25/14 , H04W88/08 , H04L25/02
CPC分类号： H04W88/08 , H04L5/001 , H04L5/0064 , H04L5/0066 , H04L5/0085 , H04L5/0091 , H04L25/0262 , H04L25/14 , H04W76/15 , Y02D70/00
摘要： A wireless device includes a processor that includes a first interface for transmitting and receiving data, a second interface that transfers data to and from the first interface, and a memory connected to the processor. The processor executes a process including acquiring carrier bandwidth information on baseband data used for wireless communication, calculating a needed data rate for transferring the baseband data between the first interface and the second interface, based on the acquired carrier bandwidth information, determining number of transfer paths for simultaneously transferring the baseband data between the first interface and the second interface, based on the calculated needed data rate, and causing the first interface and the second interface to transmit and receive the baseband data by simultaneously using the determined number of transfer paths.
摘要翻译：无线设备包括处理器，其包括用于发送和接收数据的第一接口，向第一接口传送数据和从第一接口传送数据的第二接口以及连接到处理器的存储器。处理器执行包括获取用于无线通信的基带数据的载波带宽信息的处理，基于获取的载波带宽信息，确定传送路径的数量来计算用于在第一接口和第二接口之间传送基带数据的所需数据速率用于基于所计算的所需数据速率在第一接口和第二接口之间同时传送基带数据，并且使第一接口和第二接口通过同时使用确定的传送路径数来发送和接收基带数据。

54. 发明授权

US09485025B2 Data transmission coordination over digital subscriber lines 有权
公开(公告)号：US09485025B2
公开(公告)日：2016-11-01
申请号：US14923604
申请日：2015-10-27
申请人： Futurewei Technologies, Inc.
发明人： Yuanqiu Luo , Frank Effenberger
IPC分类号： H04J14/08 , H04B10/27 , H04B3/32 , H04L25/08 , H04L25/14 , H04J3/10 , H04J3/16 , H04L12/64
CPC分类号： H04B10/27 , H04B3/32 , H04J3/10 , H04J3/1694 , H04L25/085 , H04L25/14 , H04L2012/6478
摘要： An optical management node comprising a memory comprising instructions, a processor coupled to the memory and configured execute the instructions, wherein executing the instructions causes the processor to schedule data transmissions across an electrical network between a plurality of user terminals and an optoelectrical interface by using time division multiplexing or time division multiple access based on optimization of crosstalk performance of electrical lines of the electrical network, and a transmitter coupled to the processor and configured to transmit schedule information to the optoelectrical interface via an optical network. Also disclosed is a method implemented in a management node comprising scheduling data transmissions with a plurality of user terminals across a Digital Subscriber Line (DSL) network using time division scheduling based on optimization of crosstalk performance of DSL lines of the DSL network, and transmitting schedule information to the user terminals via an optical network.

55. 发明授权

US09459650B2 Clock pulse generator for multi-phase signaling 有权
标题翻译：时钟脉冲发生器用于多相信号
公开(公告)号：US09459650B2
公开(公告)日：2016-10-04
申请号：US14496129
申请日：2014-09-25
申请人： QUALCOMM Incorporated
发明人： Xiaohua Kong , Cheng Zhong , Swarna Latha Navubothu
IPC分类号： G06F1/04 , H03K3/00 , H03K5/01 , G11C11/4076 , H04L25/02 , H04L25/14 , H03K5/00
CPC分类号： G06F1/04 , G11C11/4076 , H03K5/01 , H03K2005/00013 , H04L25/0292 , H04L25/14
摘要： A clock generator is provided that is immune to skew between bits in digital words generated by a multi-phase receiver.
摘要翻译：提供了一种时钟发生器，其免受由多相接收器产生的数字字中的位之间的偏斜。

56. 发明申请

US20160282560A1 OPTICAL DEMULTIPLEXING APPARATUS AND METHOD FOR MULTI-CARRIER DISTRIBUTION 审中-公开
标题翻译：用于多载波分配的光学解复用器和方法
公开(公告)号：US20160282560A1
公开(公告)日：2016-09-29
申请号：US15081267
申请日：2016-03-25
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人： Joon Young HUH , Sun Hyok CHANG , Hwan Seok CHUNG
IPC分类号： G02B6/293 , H04L25/14
CPC分类号： G02B6/2938 , G02B6/29316 , G02B6/29386 , H04J14/02
摘要： An optical demultiplexing apparatus and method for multi-carrier distribution are provided. The optical demultiplexing apparatus may include a demultiplexer and a carrier distributor. The optical demultiplexing apparatus and method allow efficient demultiplexing of a multi-carrier light source by using a single demultiplexer even when a carrier spacing of the light source varies.
摘要翻译：提供了一种用于多载波分配的光解复用装置和方法。光解复用装置可以包括解复用器和载波分配器。光解复用装置和方法即使当光源的载波间隔变化时，也可以通过使用单个解复用器来高效地解复用多载波光源。

57. 发明授权

US09451299B2 Method and apparatus for transmitting enhancement data in data streams 有权
标题翻译：用于在数据流中发送增强数据的方法和装置
公开(公告)号：US09451299B2
公开(公告)日：2016-09-20
申请号：US14623162
申请日：2015-02-16
申请人： TVWorks, LLC
发明人： Brian Bulkowski , Carolyn Wales , Sam Hsu , James Helman , Joseph Decker , Brock Wagenaar , Mark Vickers
IPC分类号： H04J3/06 , H04J3/04 , H04N7/173 , H04N21/236 , H04N21/434 , H04J3/12 , H04L25/14 , G06F21/62 , H04L29/06 , G06F12/14 , H04N7/088 , H04N9/82 , H04N21/235 , H04N21/262 , H04N21/435 , H04N21/462 , H04N21/654 , H04N21/81 , H04N21/8547 , H04N21/858 , H04N21/4385 , H04N21/254 , H04N21/4627 , H04J3/02 , H04J3/22 , H04N7/12 , H04N5/445 , G06F3/00 , H04N5/78 , G06F15/16 , H04N5/44
CPC分类号： H04N21/23614 , G06F12/1491 , G06F21/6218 , H04J3/047 , H04J3/0685 , H04J3/12 , H04L25/14 , H04L63/105 , H04N5/4401 , H04N7/088 , H04N7/17318 , H04N9/8205 , H04N21/235 , H04N21/23602 , H04N21/2541 , H04N21/262 , H04N21/4341 , H04N21/4344 , H04N21/435 , H04N21/4385 , H04N21/4622 , H04N21/4627 , H04N21/654 , H04N21/8126 , H04N21/8173 , H04N21/8547 , H04N21/858 , H04N21/8586
摘要： The invention provides a method and apparatus that addresses and resolves the issues currently affecting the ability to offer Enhanced TV, in particular, those issues concerning timing and synchronization, interaction with other modules in the STB, and distribution.
摘要翻译：本发明提供了解决和解决当前影响提供增强型TV的能力的问题的方法和装置，特别是有关定时和同步的问题，与STB中的其它模块的交互以及分发。

58. 发明授权

US09444612B2 Multi-wire single-ended push-pull link with data symbol transition based clocking 有权
公开(公告)号：US09444612B2
公开(公告)日：2016-09-13
申请号：US14834219
申请日：2015-08-24
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku , George Alan Wiley , Joseph Cheung
IPC分类号： H04L7/00 , H04L7/027 , G06F13/40 , G06F13/42 , H04L25/14 , H04L25/00
CPC分类号： H04L7/027 , G06F13/4072 , G06F13/4295 , H04L25/00 , H04L25/14
摘要： System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

59. 发明授权

US09413520B2 Optical transceiver and method with channel binding, clock forwarding, and integrate-and-dump receivers 有权
标题翻译：具有通道绑定，时钟转发和集成转储接收器的光收发器和方法
公开(公告)号：US09413520B2
公开(公告)日：2016-08-09
申请号：US14104534
申请日：2013-12-12
申请人： Vladimir Pelekhaty , Michael Y. Frankel
发明人： Vladimir Pelekhaty , Michael Y. Frankel
IPC分类号： H04J14/02 , H04B10/40 , H04J7/00 , H04L25/14 , H04L7/00
CPC分类号： H04L7/0075 , H04B10/40 , H04J7/00 , H04J14/02 , H04J14/0226 , H04L7/0008 , H04L25/14
摘要： An optical transceiver includes N transmitters each transmitting one of N transmitted optically bound channels; a clock forwarding mechanism to transmit a transmitted optical clock signal to an opposing optical receiver; N receivers each receiving one of N received optically bound channels; and a clock recovery mechanism to receive a received optical clock signal from the opposing optical transmitter. A method and photonically integrated system are also disclosed. The optical transceiver, method, and system optimize system design of WDM highly parallelized transceivers with optical bound channels, a simplified clocking architecture, and boosted receiver sensitivity. The optical transceiver, method, and system include clock recovery followed by data recovery and can utilize integrate-and-dump optical receivers with a recovered clock.
摘要翻译：光收发器包括N个发送器，每个发送器发送N个发送的光学绑定信道之一; 时钟转发机制，用于将发送的光时钟信号发送到相对的光接收机; N个接收器，每个接收N个接收的光学绑定信道中的一个以及时钟恢复机构，用于从相对的光发射机接收接收到的光时钟信号。还公开了一种方法和光子集成系统。光收发器，方法和系统优化了具有光限制通道的WDM高并行收发器的系统设计，简化的时钟架构和提高的接收器灵敏度。光收发器，方法和系统包括时钟恢复，随后进行数据恢复，并且可以利用具有恢复时钟的集成和转储光接收器。

60. 发明授权

US09363115B2 System and method for aligning data bits 有权
标题翻译：用于对齐数据位的系统和方法
公开(公告)号：US09363115B2
公开(公告)日：2016-06-07
申请号：US13539519
申请日：2012-07-02
申请人： Ying-Yu Hsu , Ruey-Bin Sheen , Shih-Hung Lan , Chih-Hsien Chang
发明人： Ying-Yu Hsu , Ruey-Bin Sheen , Shih-Hung Lan , Chih-Hsien Chang
IPC分类号： G06F11/07 , H04L25/14 , G06F13/16
CPC分类号： H04L25/14 , G06F13/1689
摘要： Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.
摘要翻译：公开了通过调整这些数据位的输入线的定时来对准多个数据位的系统和方法。实施例包括用于比较多组位的定时的分层结构。其他实施例包括在3D管芯堆叠架构中对准来自多个芯片的数据位。

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