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51. 发明授权

US08102690B2 Bank re-assignment in chip to reduce IR drop 有权
标题翻译：银行重新分配芯片以减少IR下降
公开(公告)号：US08102690B2
公开(公告)日：2012-01-24
申请号：US12577704
申请日：2009-10-12
申请人： Richard Michael Parent , Ryan Andrew Jurasek , Dave Eugene Chapmen
发明人： Richard Michael Parent , Ryan Andrew Jurasek , Dave Eugene Chapmen
IPC分类号： G11C5/00 , G11C8/00 , G06F11/06
CPC分类号： G11C7/1018 , G11C5/025 , G11C7/1045 , G11C2207/105
摘要： A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.
摘要翻译：在特定操作模式下降低功耗的芯片系统包括：DDR3芯片，包括：设置在DDR3芯片中心的多个焊盘; 和一组银行，每个银行都有一个特定的逻辑地址，围绕着这些垫。芯片系统还包括：耦合到DDR3芯片的时钟，用于控制数据传输速率; 以及存储器控制器，其耦合到时钟，用于根据特定操作模式来协调与相关过程的传输数据，并且用于选择性地重新分配存储体逻辑地址。

52. 发明授权

US08085569B2 Semiconductor memory device, and multi-chip package and method of operating the same 有权
标题翻译：半导体存储器件，以及多芯片封装及其操作方法
公开(公告)号：US08085569B2
公开(公告)日：2011-12-27
申请号：US12968087
申请日：2010-12-14
申请人： You Sung Kim
发明人： You Sung Kim
IPC分类号： G11C5/00 , G11C5/02 , G11C16/04
CPC分类号： G11C11/5621 , G11C2211/5641 , G11C2211/5642
摘要： Multi-chip package devices and related data programming methods are disclosed. A multi-chip package device includes one or more memory chips and a controller. The one or more memory chips include a single level cell section and a multi level cell section. The controller is configured to control a first data storing operation for storing an input data to the single level cell section and control a second data storing operation for storing the input data stored in the single level section to the multi level cell section during an idle time.
摘要翻译：公开了多芯片封装器件和相关数据编程方法。多芯片封装器件包括一个或多个存储器芯片和控制器。一个或多个存储器芯片包括单级单元部分和多级单元部分。控制器被配置为控制用于将输入数据存储到单级单元部分的第一数据存储操作，并且在空闲时间期间控制用于将存储在单级部分中的输入数据存储到多级单元部分的第二数据存储操作。

53. 发明授权

US08036012B2 Device for controlling the activity of modules of an array of memory modules 有权
标题翻译：用于控制内存模块阵列的模块活动的设备
公开(公告)号：US08036012B2
公开(公告)日：2011-10-11
申请号：US12619380
申请日：2009-11-16
申请人： Claire-Marie Lachaud , Christophe Goncalves
发明人： Claire-Marie Lachaud , Christophe Goncalves
IPC分类号： G11C11/00 , G11C5/00 , G06F12/06 , G06F13/00
CPC分类号： G06F13/4239 , G11C5/04 , Y10T29/49002
摘要： A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective memory module. The memory device includes a circuit configured to implement a NAND logic function based upon the activity signals and to output a control signal to the global controller based upon the NAND logic function.
摘要翻译：存储器设备包括存储器模块阵列，全局控制器和用于存储器模块阵列中的每个存储器模块的本地控制器，其被配置为向全局控制器递送反映相应存储器模块的活动的活动信号。存储器件包括被配置为基于活动信号实现NAND逻辑功能的电路，并且基于NAND逻辑功能将控制信号输出到全局控制器。

54. 发明授权

US07948054B2 Two-terminal nanotube devices and systems and methods of making same 有权
标题翻译：两端纳米管装置及其制造方法
公开(公告)号：US07948054B2
公开(公告)日：2011-05-24
申请号：US12861046
申请日：2010-08-23
申请人： Claude L. Bertin , Mitchell Meinhold , Steven L. Konsek , Thomas Rueckes , Max Strasburg , Frank Guo , X. M. Henry Huang , Ramesh Sivarajan
发明人： Claude L. Bertin , Mitchell Meinhold , Steven L. Konsek , Thomas Rueckes , Max Strasburg , Frank Guo , X. M. Henry Huang , Ramesh Sivarajan
IPC分类号： G11C11/56 , G11C5/00 , H01L29/00
CPC分类号： H01L27/112 , B82Y10/00 , G11C13/0002 , G11C13/025 , G11C17/16 , G11C17/165 , G11C2213/19 , G11C2213/77 , G11C2213/79 , H01L27/1052 , Y10S977/943
摘要： A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.
摘要翻译：二端存储器件包括第一和第二导电端子和纳米管制品。该制品具有至少一个纳米管，并且与第一和第二端子中的每一个的至少一部分重叠。该装置还包括与第一和第二端子中的至少一个电连通的刺激电路。电路能够将第一和第二电刺激施加到第一和第二端子中的至少一个，以在相对较高电阻和相对较低电阻之间改变第一和第二端子之间的器件的相对电阻。第一和第二端子之间的相对高的电阻对应于器件的第一状态，并且第一和第二端子之间的相对较低的电阻对应于器件的第二状态。

55. 发明申请

US20110110164A1 TRIM CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME 有权
标题翻译： TRIM电路和包含其的半导体存储器件
公开(公告)号：US20110110164A1
公开(公告)日：2011-05-12
申请号：US12912001
申请日：2010-10-26
申请人： Jae-Yong JEONG
发明人： Jae-Yong JEONG
IPC分类号： G11C5/00 , G11C16/06 , H03L5/00 , G11C29/00
CPC分类号： G11C29/02 , G11C29/026 , G11C29/028 , G11C29/44 , G11C2029/4402
摘要： A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals.
摘要翻译：修剪电路包括修剪码存储单元，全局锁存单元和本地锁存单元。修剪码存储单元存储多个修剪码，并响应于地址信号输出感测码。全局锁存单元锁存校准代码或检测代码以产生全局输出信号。通过对感测代码执行校准来生成校准代码。本地锁存单元响应于地址信号反复锁存全局输出信号以产生多个修整输出信号。

56. 发明授权

US07781862B2 Two-terminal nanotube devices and systems and methods of making same 有权
标题翻译：两端纳米管装置及其制造方法
公开(公告)号：US07781862B2
公开(公告)日：2010-08-24
申请号：US11280786
申请日：2005-11-15
申请人： Claude L. Bertin , Mitchell Meinhold , Steven L. Konsek , Thomas Ruckes , Max Strasburg , Frank Guo , X. M. Henry Huang , Ramesh Sivarajan
发明人： Claude L. Bertin , Mitchell Meinhold , Steven L. Konsek , Thomas Ruckes , Max Strasburg , Frank Guo , X. M. Henry Huang , Ramesh Sivarajan
IPC分类号： G11C11/56 , G11C5/00 , H01L29/00
CPC分类号： H01L27/112 , B82Y10/00 , G11C13/0002 , G11C13/025 , G11C17/16 , G11C17/165 , G11C2213/19 , G11C2213/77 , G11C2213/79 , H01L27/1052 , Y10S977/943
摘要： A two terminal switching device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.
摘要翻译：二端开关器件包括第一和第二导电端子和纳米管制品。该制品具有至少一个纳米管，并且与第一和第二端子中的每一个的至少一部分重叠。该装置还包括与第一和第二端子中的至少一个电连通的激励电路。该电路能够将第一和第二电刺激施加到第一和第二端子中的至少一个，以在相对较高的电阻和相对低的电阻之间改变第一和第二端子之间的器件的相对电阻。第一和第二端子之间的相对高的电阻对应于器件的第一状态，并且第一和第二端子之间的相对较低的电阻对应于器件的第二状态。

57. 发明授权

US07663903B2 Semiconductor memory device having improved voltage transmission path and driving method thereof 有权
标题翻译：具有改善的电压传输路径的半导体存储器件及其驱动方法
公开(公告)号：US07663903B2
公开(公告)日：2010-02-16
申请号：US11864604
申请日：2007-09-28
申请人： Sun-Won Kang , Seung-Duk Baek
发明人： Sun-Won Kang , Seung-Duk Baek
IPC分类号： G11C5/06 , G11C5/00 , H01L23/02 , H01L23/48
CPC分类号： G11C5/063 , H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.
摘要翻译：提供一种半导体存储器件和驱动器件的方法，该器件可以改善提供给器件的存储单元的电压信号的噪声特性。半导体存储器件包括第一半导体芯片和堆叠在第一芯片上的一个或多个第二半导体芯片。第一芯片包括用于向/从外部系统发送/接收电压信号，数据信号和控制信号的输入/输出电路。一个或多个第二半导体芯片各自包括用于存储数据的存储单元区域。第二半导体芯片通过形成在第一芯片的输入/输出电路外部的一个或多个信号路径接收至少一个信号。

58. 发明授权

US07546397B2 Systems and methods for allowing multiple devices to share the same serial lines 失效
标题翻译：允许多个设备共享相同串行线路的系统和方法
公开(公告)号：US07546397B2
公开(公告)日：2009-06-09
申请号：US11625116
申请日：2007-01-19
申请人： Theodore D. Rees , D. Stuart Smith , Dong Zheng
发明人： Theodore D. Rees , D. Stuart Smith , Dong Zheng
IPC分类号： G06F3/00 , G06F13/28 , G06F1/00 , G06F13/12 , G06F13/38 , G06F11/00 , G03F1/00 , G11C5/00 , H04N7/167
CPC分类号： G11B7/12
摘要： Methods and systems for allowing multiple devices to share the same serial lines (e.g., SDIO, SEN and SCLK) are provided. Such devices can be located, e.g., on an optical pick-up unit. Each device includes a serial interface, a device enable number (DEN) that differs from the DEN of each other device, and a plurality of registers, with at least one register being designated a device select register (DSR). The DSRs of the plurality of devices share a common address. The plurality of serial interfaces are collectively enabled and collectively disabled (e.g., via the SEN line). However, only one of the plurality of serial interfaces can be selected at one time, with the remaining of the plurality of serial interfaces being deselected. The serial interface of a device is selected when the DEN of the device is the same as the content of the DSR of the device, and deselected when the DEN of the device is not the same as the content of the DSR of the device.
摘要翻译：提供了允许多个设备共享相同串行线路（例如，SDIO，SEN和SCLK）的方法和系统。这样的设备可以位于例如光学拾取单元上。每个设备包括串行接口，与每个其他设备的DEN不同的设备使能号码（DEN）以及多个寄存器，其中至少一个寄存器被指定为设备选择寄存器（DSR）。多个设备的DSR共享公共地址。多个串行接口集体启用并集体禁用（例如，经由SEN线路）。然而，可以同时选择多个串行接口中的一个，其中多个串行接口的其余部分被取消选择。当设备的DEN与设备的DSR内容相同时，选择设备的串行接口，当设备的DEN与设备的DSR内容不同时，取消选择。

59. 发明授权

US07515451B2 Memory apparatus with a bus architecture 失效
标题翻译：具有总线架构的内存设备
公开(公告)号：US07515451B2
公开(公告)日：2009-04-07
申请号：US11856892
申请日：2007-09-18
申请人： Srdjan Djordjevic
发明人： Srdjan Djordjevic
IPC分类号： G11C5/00
CPC分类号： G11C5/00
摘要： A system comprises a board, memory units that are arranged on the board, a control unit configured to control memory access to the memory units, at least one control/address bus configured to transmit control/address signals from the control unit to a first group of the memory units, and at least one clock bus configured to transmit a clock signal from the control unit to a second group of the semiconductor memory units. A length of the at least one control/address bus corresponds to the length of the at least one clock bus. The second group of memory units comprises fewer memory units than the first group of memory units.
摘要翻译：一种系统，包括板，布置在板上的存储器单元，被配置为控制对存储器单元的存储器访问的控制单元，配置成将控制/地址信号从控制单元发送到第一组的至少一个控制/地址总线以及至少一个时钟总线，被配置为将时钟信号从控制单元发送到第二组半导体存储器单元。至少一个控制/地址总线的长度对应于至少一个时钟总线的长度。第二组存储器单元包括比第一组存储器单元更少的存储器单元。

60. 发明申请

US20090049242A1 MEMORY CARD AUTHENTICATION SYSTEM, CAPACITY SWITCHING-TYPE MEMORY CARD HOST DEVICE, CAPACITY SWITCHING-TYPE MEMORY CARD, STORAGE CAPACITY SETTING METHOD, AND STORAGE CAPACITY SETTING PROGRAM 有权
标题翻译：存储卡认证系统，容量切换型存储卡主机，容量切换型存储卡，存储容量设置方法和存储容量设置程序
公开(公告)号：US20090049242A1
公开(公告)日：2009-02-19
申请号：US12249628
申请日：2008-10-10
申请人： Hiroyuki MORO
发明人： Hiroyuki MORO
IPC分类号： G06F12/00 , G11C5/00 , G06F12/02
CPC分类号： G06F13/1694 , G06F3/0608 , G06F3/0632 , G06F3/0643 , G06F3/0644 , G06F3/0679 , G06F3/0688
摘要： A system for authenticating a memory card including a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card, a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device, and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.
摘要翻译：一种用于认证存储卡的系统，包括容量切换型存储卡主机装置，其包括容量切换通知模块，该模块通知存储卡，目的是交换信息，容量切换型存储卡主机装置处理容量切换型存储卡以及容量切换型认证模块，其对目标存储卡是容量切换型存储卡进行认证，容量切换型存储卡包括：容量切换型存储卡，其在接收到标识大容量表达式寄存器使用标志的情况下，作为容量切换型存储卡主机装置的通知，以及在容量切换型存储卡主机装置与容量切换型存储卡之间发送和接收数据的总线。

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