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51. 发明授权

US09520367B2 Trenched Faraday shielding 有权
标题翻译：倾斜的法拉第屏蔽
公开(公告)号：US09520367B2
公开(公告)日：2016-12-13
申请号：US14463982
申请日：2014-08-20
申请人： Zihao M. Gao , David C. Burdeaux , Wayne R. Burger , Robert A. Pryor , Philippe Renaud
发明人： Zihao M. Gao , David C. Burdeaux , Wayne R. Burger , Robert A. Pryor , Philippe Renaud
IPC分类号： H01L23/60 , H01L29/78 , H01L29/66 , H01L29/06 , H01L21/283 , H01L21/306 , H01L21/71 , H01L29/40 , H01L29/417 , H01L29/08 , H01L21/265 , H01L29/10
CPC分类号： H01L23/60 , H01L21/26586 , H01L21/283 , H01L21/30604 , H01L21/71 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/7817 , H01L29/7823 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.
摘要翻译：一种器件包括具有沟槽的表面的半导体衬底，由半导体衬底支撑的第一和第二导电端子，由第一和第二导电端子之间的半导体衬底支撑的控制电极，并且被配置为在第一和第二导电端子之间的运行期间控制电荷载流子的流动第一和第二导电端子以及由半导体衬底支撑并设置在控制电极和第二导电端子之间的法拉第屏蔽。法拉第屏蔽的至少一部分设置在沟槽中。

52. 发明授权

US09048277B2 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US09048277B2
公开(公告)日：2015-06-02
申请号：US13759251
申请日：2013-02-05
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiaki Oikawa , Shingo Eguchi , Shunpei Yamazaki
IPC分类号： H01L21/71 , H01L23/29 , H01L23/31
CPC分类号： H01L21/71 , H01L23/293 , H01L23/3157 , H01L2924/0002 , H01L2924/12044 , H01L2924/19041 , H01L2924/00
摘要： To reduce defects of a semiconductor device, such as defects in shape and characteristic due to external stress and electrostatic discharge. To provide a highly reliable semiconductor device. In addition, to increase manufacturing yield of a semiconductor device by reducing the above defects in the manufacturing process. The semiconductor device includes a semiconductor integrated circuit sandwiched by impact resistance layers against external stress and an impact diffusion layer diffusing the impact and a conductive layer covering the semiconductor integrated circuit. With the use of the conductive layer covering the semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit can be prevented.
摘要翻译：为了减少半导体器件的缺陷，例如由于外部应力和静电放电引起的形状和特性的缺陷。提供高度可靠的半导体器件。此外，为了通过减少制造过程中的上述缺陷来提高半导体器件的制造成品率。该半导体器件包括夹在抗冲击电阻层和外部应力之间的半导体集成电路和扩散冲击的冲击扩散层和覆盖半导体集成电路的导电层。通过使用覆盖半导体集成电路的导电层，可以防止由于半导体集成电路的静电放电引起的静电击穿（电路的故障或半导体元件的损坏）。

53. 发明申请

US20150054126A1 METHOD AND SYSTEM FOR A METAL FINGER CAPACITOR WITH A TRIPLET REPEATING SEQUENCE INCORPORATING A METAL UNDERPASS 有权
标题翻译：金属指针电容器的方法和系统，具有并入金属底层的TRIPLET重复序列
公开(公告)号：US20150054126A1
公开(公告)日：2015-02-26
申请号：US14319747
申请日：2014-06-30
申请人： Maxlinear, Inc.
发明人： Weizhong Cai
IPC分类号： H01L49/02 , H01G4/002 , H01L21/71
CPC分类号： H01G4/002 , H01G4/005 , H01G4/228 , H01L23/5223 , H01L28/88 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： Methods and systems for a metal finger capacitor with a triplet repeating sequence incorporating a metal underpass may comprise repeating triplet capacitors integrated on a semiconductor die. The capacitors may comprise a first set of interconnected metal fingers comprising a first terminal of a first capacitor, a second set of interconnected metal fingers comprising a first terminal of a second capacitor, and a third set of interconnected metal fingers comprising a common node that surrounds the first and second sets of interconnected metal fingers. The common node may comprise a second terminal of the capacitors. A repeating pattern of fingers may be: (third set/second set/third set/first set . . . ). The repeating pattern of metal fingers may be arranged in two parallel rows to mitigate variations in the semiconductor die. The interconnected metal fingers may comprise first and second metal layers formed on the semiconductor die.
摘要翻译：具有并入金属通道的三重重复序列的金属制电容器的方法和系统可以包括集成在半导体管芯上的重复三重态电容器。电容器可以包括第一组互连金属指，其包括第一电容器的第一端子，第二组互连的金属指，其包括第二电容器的第一端子以及第三组相互连接的金属指状物，其包括围绕第一组和第二组相互连接的金属指。公共节点可以包括电容器的第二端子。手指的重复模式可以是：（第三组/第二组/第三组/第一组）...。金属指的重复图案可以布置成两排平行，以减轻半导体管芯的变化。互连的金属指可以包括形成在半导体管芯上的第一和第二金属层。

54. 发明申请

US20140264772A1 Shielding for Through-Silicon-Via 有权
标题翻译：屏蔽通硅片
公开(公告)号：US20140264772A1
公开(公告)日：2014-09-18
申请号：US13795035
申请日：2013-03-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
发明人： Jaw-Juinn Horng , Chung-Peng Hsieh
IPC分类号： H01L23/552 , H01L21/71
CPC分类号： H01L23/552 , H01L23/481 , H01L23/528 , H01L23/5384 , H01L23/5386 , H01L23/585 , H01L25/0657 , H01L2225/06513 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： 3D integrated circuit devices include first and second semiconductor bodies. The first semiconductor body has an active area, a through-silicon-via outside the active area, and two or more disjoint guard rings. The first guard ring encircles the via. The second guard ring encircles the active area, but not the via. The guard rings can reduce the noise coupling coefficient between the via and the active area to −60 dB or less at 3 GHz and 20 μm spacing.
摘要翻译： 3D集成电路器件包括第一和第二半导体本体。第一半导体本体具有有源区域，有源区域外的穿硅通孔以及两个或更多个不相交的保护环。第一个护环环绕通道。第二个保护环环绕活动区域，但不包括通道。保护环可以将通孔和有源区域之间的噪声耦合系数降低到3 GHz和20μm间距的-60 dB或更小。

55. 发明申请

US20140239484A1 METHOD FOR FORMING SINTERED SILVER COATING FILM, BAKING APPARATUS, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成烧结银涂膜的方法，烘烤装置和半导体装置
公开(公告)号：US20140239484A1
公开(公告)日：2014-08-28
申请号：US14184640
申请日：2014-02-19
申请人： Tokyo Electron Limited
发明人： Kenji MATSUDA , Dai SHINOZAKI , Muneo HARADA , Yoshinobu MITANO , Michikazu NAKAMURA , Itaru IIDA , Shinjiro WATANABE
IPC分类号： H01L21/71 , F27D21/00 , F27D11/02 , F27D19/00 , H01L23/373 , F27D7/02
CPC分类号： H01L23/3736 , F27B17/0025 , H01L21/4871 , H01L21/561 , H01L21/67109 , H01L21/67248 , H01L21/67253 , H01L23/3735 , H01L2924/0002 , Y02P10/143 , H01L2924/00
摘要： In a method for forming a sintered silver coating film, for use as a heat spreader, on a semiconductor substrate or a semiconductor package, a coating film of an ink or paste containing silver nanoparticles is formed on one surface of the semiconductor substrate or the substrate package. Further, the coating film is sintered by heating the coating film under an atmosphere of a humidity of 30% to 50% RH (30° C.) by a ventilation oven.
摘要翻译：在半导体衬底或半导体封装上形成用作散热器的烧结银涂膜的方法中，在半导体衬底或衬底的一个表面上形成含有银纳米颗粒的油墨或糊料的涂膜包。此外，通过通风烘箱在湿气为30％〜50％RH（30℃）的气氛下加热涂膜来烧结涂膜。

56. 发明申请

US20140091441A1 IC WAFER HAVING ELECTROMAGNETIC SHIELDING EFFECTS AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：具有电磁屏蔽效应的IC制造方法及其制造方法
公开(公告)号：US20140091441A1
公开(公告)日：2014-04-03
申请号：US14092795
申请日：2013-11-27
申请人： XINTEC INC.
发明人： Yao-Hsiang CHEN , Tsang-Yu LIU , Yen-Shih HO , Shu-Ming CHANG
IPC分类号： H01L23/552 , H01L23/00 , H01L21/71
CPC分类号： H01L23/552 , H01L21/71 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0346 , H01L2224/0361 , H01L2224/0401 , H01L2224/05572 , H01L2224/06155 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13144 , H01L2924/00013 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic shielding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.
摘要翻译： IC晶片和IC晶片的制造方法，IC晶片包括具有多个焊盘和设置在其上的绝缘层的集成电路层，多个贯穿相应于焊盘的绝缘层的通孔，分别用于封装层的注入，以及形成在绝缘层的顶表面上并与用于电磁屏蔽的集成电路层的焊盘电隔离的电磁屏蔽层。因此，集成电路不需要任何进一步的屏蔽掩模，从而简化制造。此外，通孔的设计有助于进一步的包装过程。

57. 发明授权

US08633051B2 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US08633051B2
公开(公告)日：2014-01-21
申请号：US12859446
申请日：2010-08-19
申请人： Yoshiyuki Kurokawa , Takayuki Ikeda , Munehiro Kozuma , Hikaru Tamura , Kazuko Yamawaki , Takashi Hamada , Shunpei Yamazaki
发明人： Yoshiyuki Kurokawa , Takayuki Ikeda , Munehiro Kozuma , Hikaru Tamura , Kazuko Yamawaki , Takashi Hamada , Shunpei Yamazaki
IPC分类号： H01L31/0232 , H01L21/71
CPC分类号： G09F9/33 , H01L31/0203 , H01L31/02325
摘要： An object is to prevent a reduction of definition (or resolution) (a peripheral blur) caused when reflected light enters a photoelectric conversion element arranged at a periphery of a photoelectric conversion element arranged at a predetermined address. A semiconductor device is manufactured through the steps of: forming a structure having a first light-transmitting substrate, a plurality of photoelectric conversion elements over the first light-transmitting substrate, a second light-transmitting substrate provided so as to face the plurality of photoelectric conversion elements, a sealant arranged so as to bond the first light-transmitting substrate and the second light-transmitting substrate and surround the plurality of photoelectric conversion elements; and thinning the first light-transmitting substrate by wet etching.
摘要翻译：目的是防止当反射光进入布置在布置在预定地址处的光电转换元件的周围的光电转换元件时引起的定义（或分辨率）（外围模糊）的降低。通过以下步骤制造半导体器件：在第一透光衬底上形成具有第一透光衬底，多个光电转换元件的结构，设置成面对多个光电转换元件的第二透光衬底转换元件，密封剂，其被布置成结合第一透光性基板和第二透光性基板，并且包围多个光电转换元件; 并通过湿蚀刻使第一透光衬底变薄。

58. 发明申请

US20130149816A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20130149816A1
公开(公告)日：2013-06-13
申请号：US13759251
申请日：2013-02-05
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD
发明人： Yoshiaki OIKAWA , Shingo EGUCHI , Shunpei YAMAZAKI
IPC分类号： H01L21/71
CPC分类号： H01L21/71 , H01L23/293 , H01L23/3157 , H01L2924/0002 , H01L2924/12044 , H01L2924/19041 , H01L2924/00
摘要： To reduce defects of a semiconductor device, such as defects in shape and characteristic due to external stress and electrostatic discharge. To provide a highly reliable semiconductor device. In addition, to increase manufacturing yield of a semiconductor device by reducing the above defects in the manufacturing process. The semiconductor device includes a semiconductor integrated circuit sandwiched by impact resistance layers against external stress and an impact diffusion layer diffusing the impact and a conductive layer covering the semiconductor integrated circuit. With the use of the conductive layer covering the semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit can be prevented.

59. 发明授权

US08357561B2 Method of fabricating backside illuminated image sensor 有权
标题翻译：制造背面照明图像传感器的方法
公开(公告)号：US08357561B2
公开(公告)日：2013-01-22
申请号：US13044407
申请日：2011-03-09
申请人： Shih-Chi Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
发明人： Shih-Chi Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
IPC分类号： H01L31/18 , H01L21/71 , H01L31/0232
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14621 , H01L27/14627 , Y10S438/977
摘要： A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference.
摘要翻译：提供了制造背面照明图像传感器的方法。示例性方法可以包括提供具有前表面和后表面的基底; 在基板的前表面形成对准标记，其中对准标记可从后表面对准检测; 并且通过从背面进行配准并使用对准标记作为基准，从背面处理基板。

60. 发明申请

US20120289062A1 Liner Formation in 3DIC Structures 有权
标题翻译： 3DIC结构中的衬板形成
公开(公告)号：US20120289062A1
公开(公告)日：2012-11-15
申请号：US13562101
申请日：2012-07-30
申请人： Ching-Yu Lo , Hung-Jung Tu , Hai-Ching Chen , Tien-I Bao , Wen-Chih Chiou , Chen-Hua Yu
发明人： Ching-Yu Lo , Hung-Jung Tu , Hai-Ching Chen , Tien-I Bao , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： H01L21/71
CPC分类号： H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L2221/68372 , H01L2224/0557 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.
摘要翻译：集成电路结构包括半导体衬底; 贯穿半导体衬底的贯通半导体通孔（TSV）开口; 和TSV开口的TSV衬管。 TSV衬套包括在TSV开口的侧壁上的侧壁部分和TSV开口底部的底部。 TSV衬管的底部部分的底部高度大于TSV衬套的侧壁部分的中间厚度。

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