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51. 发明申请

US20170041086A1 DATA TRANSMISSION APPARATUS FOR CHANGING CLOCK SIGNAL AT RUNTIME AND DATA INTERFACE SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：用于在运行期间更改时钟信号的数据传输装置和包括其的数据接口系统
公开(公告)号：US20170041086A1
公开(公告)日：2017-02-09
申请号：US15223524
申请日：2016-07-29
申请人： Samsung Electronics Co., Ltd.
发明人： Seung Beom PARK , Hong Sik PARK , Jong Hyup LEE
IPC分类号： H04B15/02 , H04B17/00 , H03L7/07
CPC分类号： H04B15/02 , H03L7/22 , H04B17/0085
摘要： In an example embodiment, a data transmission apparatus includes a transmission link module configured to generate a reference clock signal and a transmission D-PHY module. The transmission D-PHY module includes a first phase locked loop configured to receive the reference clock signal, and generate a first clock signal. The transmission D-PHY module further includes a second phase locked loop configured to receive the reference clock signal, and generate a second clock signal having a different frequency than the first clock signal. The transmission D-PHY module further includes a multiplexer configured to select and output one of the first and second clock signals as a clock signal according to a selection signal. The transmission D-PHY module further includes a data transmitter configured to convert parallel data into serial data in response to the clock signal for transmission to a receiver.
摘要翻译：在示例实施例中，数据传输装置包括被配置为产生参考时钟信号和传输D-PHY模块的传输链路模块。传输D-PHY模块包括被配置为接收参考时钟信号并产生第一时钟信号的第一锁相环。传输D-PHY模块还包括被配置为接收参考时钟信号并产生具有与第一时钟信号不同的频率的第二时钟信号的第二锁相环。传输D-PHY模块还包括多路复用器，其被配置为根据选择信号选择并输出第一和第二时钟信号中的一个作为时钟信号。传输D-PHY模块还包括数据发射机，其被配置为响应于时钟信号将并行数据转换为串行数据，以传输到接收机。

52. 发明申请

US20170019112A1 APPARATUS AND METHOD FOR CLOCK SYNCHRONIZATION FOR INTER-DIE SYNCHRONIZED DATA TRANSFER 审中-公开
标题翻译：用于内部同步数据传输的时钟同步的装置和方法
公开(公告)号：US20170019112A1
公开(公告)日：2017-01-19
申请号：US15214364
申请日：2016-07-19
申请人： Intel Corporation
发明人： Shenggao Li , Stefan Rusu
IPC分类号： H03L7/07 , G06F13/40 , H03L7/081 , G06F1/12 , H01L23/48 , H03L7/091
CPC分类号： H03L7/00 , G06F1/12 , G06F13/4027 , H01L23/481 , H01L25/0657 , H01L2224/48137 , H01L2224/49175 , H01L2225/06541 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0012 , H04L7/0025 , Y02D10/14 , Y02D10/151
摘要： Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.
摘要翻译：描述了一种用于时钟同步的装置。该装置包括一对互连; 包括具有耦合到所述互连中的一个的输出的第一相位内插器的第一管芯; 以及第二管芯，其中所述一对互连件将所述第一管芯连接到所述第二管芯。

53. 发明授权

US09496916B2 Semiconductor device, receiver, transmitter, transceiver and communication system 有权
标题翻译：半导体器件，接收器，发射器，收发器和通信系统
公开(公告)号：US09496916B2
公开(公告)日：2016-11-15
申请号：US14332657
申请日：2014-07-16
申请人： Renesas Electronics Corporation
发明人： Masao Nakadaira
IPC分类号： H04B1/7073 , H03L7/085 , H04B1/02 , H04B1/06 , H04B1/38 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/089 , H03L7/091
CPC分类号： H04B1/7073 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/085 , H03L7/089 , H03L7/091 , H04B1/02 , H04B1/06 , H04B1/38
摘要： A semiconductor device, includes a clock and data recovery unit to which a receive signal is inputted and which extracts, based on an operation clock signal, a clock signal and a data signal from the receive signal, a frequency error adjusting unit which generates a frequency error signal indicating a frequency error between the clock signal extracted from the receive signal and the operation clock signal, an operation clock generation unit which controls, based on the frequency error signal, a frequency of the operation clock signal, and a Spread Spectrum Clock Generator (SSCG) unit which varies the frequency of the operation clock signal by the SSCG unit based on the frequency error signal.
摘要翻译：一种半导体器件，包括：时钟和数据恢复单元，接收信号输入到该时钟和数据恢复单元，其基于操作时钟信号从接收信号中提取时钟信号和数据信号;频率误差调整单元，其产生频率误差信号，指示从接收信号提取的时钟信号与操作时钟信号之间的频率误差;操作时钟产生单元，其基于频率误差信号控制操作时钟信号的频率;以及扩频时钟发生器（SSCG）单元，其基于频率误差信号改变SSCG单元的操作时钟信号的频率。

54. 发明授权

US09461656B2 Injection-locked phase locked loop circuits using delay locked loops 有权
标题翻译：使用延迟锁定环的注入锁相环路电路
公开(公告)号：US09461656B2
公开(公告)日：2016-10-04
申请号：US14558072
申请日：2014-12-02
申请人： Samsung Electronics Co., Ltd.
发明人： Hye-Yoon Joo , Seung-Jun Bae , Young-Soo Sohn , Ho-Sung Song , Jeong-Don Ihm
IPC分类号： H03L7/06 , H03L7/087 , H03L7/07 , H03L7/083 , H03L7/099 , G11C7/22
CPC分类号： H03L7/087 , G11C7/222 , H03L7/07 , H03L7/083 , H03L7/0995
摘要： An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.
摘要翻译：注射锁相环（ILPLL）电路包括延迟锁定环（DLL）和ILPLL。 DLL被配置为通过对参考时钟执行延迟锁定操作来生成DLL时钟。 ILPLL包括压控振荡器（VCO），并且被配置为通过对参考时钟执行注入同步锁相操作来产生输出时钟。将DLL时钟作为VCO的注入时钟注入到VCO中。

55. 发明申请

US20160204784A1 System and Method for Synchronizing Multiple Oscillators Using Reduced Frequency Signaling 有权
标题翻译：使用降频信号同步多个振荡器的系统和方法
公开(公告)号：US20160204784A1
公开(公告)日：2016-07-14
申请号：US14597039
申请日：2015-01-14
申请人： Infineon Technologies AG
发明人： Saverio Trotta , Reinhard-Wolfgang Jungmaier
IPC分类号： H03L7/07 , H03L7/099 , H01Q3/30 , H03L7/093
CPC分类号： H03L7/07 , H01Q3/30 , H03L7/093 , H03L7/099
摘要： An embodiment method for voltage-controlled oscillator (VCO) control includes detecting a first VCO output signal of a first VCO. The first VCO output signal has a first VCO output frequency. The method also includes determining a first down-scaled signal in accordance with the first VCO output signal. The first down-scaled signal has a first down-scaled frequency that is reduced by a fixed ratio relative to a current value of the first VCO output frequency. The method also includes modifying the first VCO output frequency using a first phase lock loop (PLL) in accordance with the first down-scaled signal and an oscillating reference signal, and detecting a second VCO output signal of a second VCO. The second VCO output signal has a second VCO output frequency. The method also includes modifying the second VCO output frequency in accordance with the second VCO output signal and the first down-scaled signal.
摘要翻译：压控振荡器（VCO）控制的实施例方法包括检测第一VCO的第一VCO输出信号。第一个VCO输出信号具有第一个VCO输出频率。该方法还包括根据第一VCO输出信号来确定第一缩小信号。第一缩小信号具有相对于第一VCO输出频率的当前值降低固定比率的第一降频频率。该方法还包括使用根据第一缩小信号和振荡参考信号的第一锁相环（PLL）来修改第一VCO输出频率，以及检测第二VCO的第二VCO输出信号。第二个VCO输出信号具有第二个VCO输出频率。该方法还包括根据第二VCO输出信号和第一缩小信号修改第二VCO输出频率。

56. 发明授权

US09374098B2 Transmitter serializer latency trim 有权
标题翻译：发送器串行器延迟修整
公开(公告)号：US09374098B2
公开(公告)日：2016-06-21
申请号：US14172550
申请日：2014-02-04
申请人： GLOBALFOUNDRIES U.S. 2 LLC
发明人： Leonard R. Chieco , Frank R. Keyser, III , Michael A Sorna
IPC分类号： H04J3/06 , H03L7/07 , H04L7/10 , H04L7/00 , H03L7/081 , H03M9/00 , H04L1/00 , G06F1/12
CPC分类号： H03L7/07 , G06F1/12 , H03L7/0814 , H03M9/00 , H04L1/00 , H04L7/0008 , H04L7/0091 , H04L7/10
摘要： A system and method for transmitting includes a plurality of multiplexers each configured to combine a pseudo random bit sequence (PRBS) with at least one input stream according to the data control clock. At least one storage device is coupled to an output of each of the plurality of multiplexers and is configured to latch data according to the data control clock. An output multiplexer is coupled to each of the at least one storage device and is configured to select between storage paths according to the data serializer clock. A PRBS checker is configured to compare a PRBS pattern on an output of the output multiplexer with a predicted PRBS pattern. A phase rotator is configured to adjust the data serializer clock based upon the comparison of the PRBS checker to reduce latency of the transmitter.
摘要翻译：用于发送的系统和方法包括多个多路复用器，每个复用器被配置为根据数据控制时钟将伪随机比特序列（PRBS）与至少一个输入流组合。至少一个存储设备耦合到多个多路复用器中的每一个的输出，并且被配置为根据数据控制时钟锁存数据。输出多路复用器耦合到所述至少一个存储设备中的每一个，并且被配置为根据数据串行器时钟在存储路径之间进行选择。 PRBS检查器被配置为将输出多路复用器的输出上的PRBS模式与预测的PRBS模式进行比较。相位旋转器被配置为基于PRBS检查器的比较来调整数据串行器时钟，以减少发射机的等待时间。

57. 发明授权

US09350360B2 Systems and methods for configuring a semiconductor device 有权
标题翻译：用于配置半导体器件的系统和方法
公开(公告)号：US09350360B2
公开(公告)日：2016-05-24
申请号：US14852747
申请日：2015-09-14
申请人： Marvell World Trade Ltd.
发明人： Sehat Sutardja
IPC分类号： H03L7/00 , H03L1/02 , G11C5/00 , G11C5/14 , H01L23/10 , H01L23/31 , H01L23/34 , H03B5/04 , H03B5/36 , H03L1/04 , H03L7/07 , H03L7/099 , H03L7/197 , H01L23/522 , H03L7/089
CPC分类号： H03L1/026 , G11C5/00 , G11C5/143 , H01L23/10 , H01L23/315 , H01L23/345 , H01L23/5227 , H01L2224/05553 , H01L2224/48247 , H01L2224/49175 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H03B5/04 , H03B5/36 , H03L1/027 , H03L1/04 , H03L7/07 , H03L7/0891 , H03L7/099 , H03L7/1976 , H01L2924/00
摘要： A system for configuring a semiconductor device to generate an output signal. The system includes a temperature sensor configured to sense a plurality of operating temperatures of the semiconductor device, the plurality of operating temperatures including at least a first operating temperature and a second operating temperature. A controller is configured to determine a plurality of operating frequencies of the output signal at respective operating temperatures of the plurality of operating temperatures. The plurality of operating frequencies include a first operating frequency of the output signal when the semiconductor device is at the first operating temperature and a second operating frequency of the output signal when the semiconductor device is at the second operating temperature. Memory is configured to store calibration information that associates each of the plurality of operating temperatures of the semiconductor device with respective operating frequencies of the plurality of operating frequencies.
摘要翻译：一种用于配置半导体器件以产生输出信号的系统。该系统包括被配置为感测半导体器件的多个工作温度的温度传感器，多个工作温度至少包括第一工作温度和第二工作温度。控制器被配置为在多个操作温度的相应操作温度下确定输出信号的多个工作频率。当半导体器件处于第一工作温度时，多个工作频率包括输出信号的第一工作频率和当半导体器件处于第二工作温度时的输出信号的第二工作频率。存储器被配置为存储将半导体器件的多个操作温度中的每一个与多个工作频率的相应工作频率相关联的校准信息。

58. 发明授权

US09344269B2 Receiving circuit 有权
标题翻译：接收电路
公开(公告)号：US09344269B2
公开(公告)日：2016-05-17
申请号：US14681794
申请日：2015-04-08
申请人： FUJITSU LIMITED
发明人： Takayuki Shibasaki
IPC分类号： H04L7/033 , H03L7/089 , H03B5/12 , H03L7/07 , H03L7/093
CPC分类号： H04L7/033 , H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/124 , H03L7/07 , H03L7/0891 , H03L7/093 , H04L7/0331 , H04L25/14
摘要： A receiving circuit includes circuits arranged in parallel, each circuits including a voltage-controlled-oscillator (VCO) configured to generate a clock having an oscillation frequency according to an inductor and a capacitor, and a gain circuit. Each circuit is configured to sample a piece of input data with an output clock of the VCO and adjust the oscillation frequency of the VCO based on a phase difference and a frequency difference between the piece of input data and the output clock, thereby recovering data and a clock based on the piece of input data. The gain circuit is configured to adjust ratios of gains of up and down of the oscillation frequency of the VCO in a loop in each circuit arranged adjacent to each other, based on a phase difference between the pieces of input data and a phase difference between the output clocks of the respective circuits.
摘要翻译：接收电路包括并联布置的电路，每个电路包括被配置为产生具有根据电感器和电容器的振荡频率的时钟的压控振荡器（VCO）和增益电路。每个电路被配置为利用VCO的输出时钟对一条输入数据进行采样，并且基于输入数据和输出时钟之间的相位差和频率差来调整VCO的振荡频率，从而恢复数据和基于输入数据的时钟。所述增益电路被配置为基于所述输入数据之间的相位差和所述输入数据之间的相位差来调整在彼此相邻布置的每个电路中的环路中的所述VCO的振荡频率的上升和下降的比率各个电路的输出时钟。

59. 发明授权

US09287853B2 Signal conversion circuit, PLL circuit, delay adjustment circuit, and phase control circuit 有权
标题翻译：信号转换电路，PLL电路，延迟调整电路和相位控制电路
公开(公告)号：US09287853B2
公开(公告)日：2016-03-15
申请号：US14122822
申请日：2012-05-23
申请人： Toru Nakura , Kunihiro Asada
发明人： Toru Nakura , Kunihiro Asada
IPC分类号： H03L7/06 , H03K3/01 , H03L7/099 , H03K5/153 , G04F10/00 , H03L7/07 , H03L7/081 , H03L7/089
CPC分类号： H03K3/01 , G04F10/005 , H03K5/153 , H03L7/07 , H03L7/0812 , H03L7/0816 , H03L7/089 , H03L7/099
摘要： A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.
摘要翻译：信号转换电路，PLL电路，延迟控制电路和用于促进小型化和减少量化噪声的相位控制电路。 TSTC不需要电容器Cm的低通滤波器，具有通常所需的大的布局面积，用于转换脉冲宽度到电压，从而促进小型化和降低成本。与传统的数字PLL电路相比，TSTC 8产生适合于脉冲信号传输边界处的过渡状态的模拟电压，这降低了量化噪声。

60. 发明授权

US09203416B2 Compensation of slow time-varying variations in voltage controlled oscillator (VCO) frequency in cellular transceivers 有权
标题翻译：在蜂窝收发器中压控振荡器（VCO）频率的慢时变变化的补偿
公开(公告)号：US09203416B2
公开(公告)日：2015-12-01
申请号：US13914486
申请日：2013-06-10
申请人： Broadcom Corporation
发明人： Dmitriy Rozenblit , Rahul Magoon
IPC分类号： H04B1/403 , H03L7/07 , H03L7/099 , H03L7/08
CPC分类号： H03L7/08 , H03L7/099 , H03L7/102 , H03L7/183 , H03L2207/06
摘要： Various configurations and arrangements of systems and methods for compensating for variations in VCO output frequencies are described. A system in accordance with the disclosure can include an oscillator circuit including an oscillator, a first variable capacitance diode coupled to the oscillator and a second variable capacitance diode coupled to the oscillator. The system further includes a voltage source configured to apply a first voltage to the oscillator circuit to cause the output signal to comprise a selected frequency, the selected frequency being based on a received reference voltage. The system further includes a controller circuit configured to compare an operating voltage of the oscillator to the reference voltage while the first voltage is applied to the oscillator; and apply a second voltage to the oscillator circuit based on the comparison. The second voltage compensates for a difference between the reference voltage and the first voltage.
摘要翻译：描述用于补偿VCO输出频率变化的系统和方法的各种配置和布置。根据本公开的系统可以包括振荡器电路，其包括振荡器，耦合到振荡器的第一可变电容二极管和耦合到振荡器的第二可变电容二极管。该系统还包括被配置为向振荡器电路施加第一电压以使输出信号包括所选择的频率的电压源，所选频率基于所接收的参考电压。该系统还包括控制器电路，其被配置为在将第一电压施加到振荡器的同时将振荡器的工作电压与参考电压进行比较; 并根据比较对振荡电路施加第二电压。第二电压补偿参考电压和第一电压之间的差。

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