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61. 发明申请

US20060132250A1 Voltage- and temperature-compensated RC oscillator circuit 有权
公开(公告)号：US20060132250A1
公开(公告)日：2006-06-22
申请号：US11022331
申请日：2004-12-21
申请人： Gregory Bakker
发明人： Gregory Bakker
IPC分类号： H03B5/20
CPC分类号： H03K3/0231 , H03K3/011 , H03L1/022
摘要： An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

62. 发明授权

US06885218B1 Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA 有权
标题翻译：并行可编程反熔丝现场可编程门阵列器件（FPGA）以及反熔丝FPGA的编程和测试方法
公开(公告)号：US06885218B1
公开(公告)日：2005-04-26
申请号：US10267917
申请日：2002-10-08
申请人： Shin-Nan Sun , Wayne W. Wong
发明人： Shin-Nan Sun , Wayne W. Wong
IPC分类号： H03K19/177
CPC分类号： H03K19/17776 , H03K19/17728 , H03K19/1778
摘要： The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.
摘要翻译：本发明包括用于在多瓦片现场可编程门阵列（FPGA）中同时编程多个反熔丝的装置和方法。本发明包括具有多个具有可编程元件的逻辑模块的FPGA。逻辑模块被划分成多个单独可编程的组，并且隔离装置可以耦合在单独可编程的逻辑模块组之间，使得多个单独可编程逻辑模块中的每一个中的每个可编程元件可以被同时编程。

63. 发明授权

US06853055B1 Radiation shielding die carrier package 有权
标题翻译：辐射屏蔽模具载体封装
公开(公告)号：US06853055B1
公开(公告)日：2005-02-08
申请号：US10724531
申请日：2003-11-26
申请人： Raymond Kuang
发明人： Raymond Kuang
IPC分类号： H01L23/04 , H01L23/047 , H01L23/552
CPC分类号： H01L23/552 , H01L23/04 , H01L23/047 , H01L24/45 , H01L24/48 , H01L2224/451 , H01L2224/48235 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15192 , H01L2924/16152 , H01L2924/1616 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor die carrier includes a radiation shielding base having a radiation shielding integrated base flange extending orthogonally from an upper surface of the base, the integrated base flange having an upper surface. A substrate is disposed on the radiation shielding base and around the integrated base flange, the substrate has an uppermost tier with an upper surface that is not higher than the upper surface of said integrated base flange. A radiation shielding seal lid has a radiation shielding integrated seal lid flange, the radiation shielding integrated seal lid flange has a lower surface disposed on the upper surface of the uppermost tier of the substrate.
摘要翻译：半导体管芯载体包括辐射屏蔽基底，该辐射屏蔽基底具有从基底的上表面垂直延伸的辐射屏蔽集成基底凸缘，所述一体化基底凸缘具有上表面。衬底设置在辐射屏蔽基底上并围绕一体化的基底凸缘，衬底具有最高层，其上表面不高于所述集成的基底凸缘的上表面。辐射屏蔽密封盖具有辐射屏蔽集成密封盖凸缘，辐射屏蔽一体化密封盖凸缘具有设置在基板最上层的上表面上的下表面。

64. 发明授权

US06838903B1 Block connector splitting in logic block of a field programmable gate array 有权
标题翻译：在现场可编程门阵列的逻辑块中的块连接器分离
公开(公告)号：US06838903B1
公开(公告)日：2005-01-04
申请号：US10608454
申请日：2003-06-26
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A logic block in a field programmable gate array comprises a plurality of clusters of logic devices. At least one of the logic devices in each of the clusters has an input or an output. A first set of interconnect conductors enters the logic block from a first side and forming a programmable intersection with the input or the output of at least one of the logic devices in each of the clusters. A second set of interconnect conductors enters the logic block from a second side and forming a programmable intersection with the input or output of one of the logic devices in each cluster, the first set of interconnect conductors forming a pairwise hardwired connection with the second set of interconnect conductors. An interconnect conductor splitting extension is disposed between the first set of interconnect conductors and the second set of interconnect conductors.
摘要翻译：现场可编程门阵列中的逻辑块包括多个逻辑器件群集。每个集群中的至少一个逻辑设备具有输入或输出。第一组互连导体从第一侧进入逻辑块，并且形成与每个簇中的至少一个逻辑器件的输入或输出的可编程交叉。第二组互连导体从第二侧进入逻辑块并且与每个簇中的逻辑器件中的一个的输入或输出形成可编程交叉，第一组互连导体与第二组互连导体形成成对的硬连线连接互连导体。互连导体分裂延伸部设置在第一组互连导体和第二组互连导体之间。

65. 发明授权

US06838902B1 Synchronous first-in/first-out block memory for a field programmable gate array 有权
公开(公告)号：US06838902B1
公开(公告)日：2005-01-04
申请号：US10448259
申请日：2003-05-28
申请人： Daniel Elftmann , Theodore Speers , Arunangshu Kundu
发明人： Daniel Elftmann , Theodore Speers , Arunangshu Kundu
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/1778
摘要： The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.

66. 发明授权

US06838899B2 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array 有权
标题翻译：辐射硬化静态随机存取存储器现场可编程门阵列中误差检测和校正的装置和方法
公开(公告)号：US06838899B2
公开(公告)日：2005-01-04
申请号：US10335234
申请日：2002-12-30
申请人： William C. Plants
发明人： William C. Plants
IPC分类号： G06F11/10 , G11C5/00 , G11C11/412 , H03K19/003
CPC分类号： G06F11/1008 , G11C5/005 , G11C11/4125 , H01L27/118 , H03K19/00338 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).The present system also comprises a method for correcting errors in a programmable logic device having configuration data to program the programmable logic device. The method comprises a background reading of the configuration data. Next, the configuration data is analyzed for errors. Finally, the configuration data is then corrected and the configuration data is rewritten if errors are located.
摘要翻译：本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。提供配置数据的配置数据线控制逻辑模块和路由资源的编程。耦合到配置数据线的错误校正电路分析和校正由于单个事件不正（SEU）可能发生的配置数据中的任何错误。本系统还包括用于校正具有配置数据的可编程逻辑器件中的错误的方法对可编程逻辑器件进行编程。该方法包括配置数据的背景读取。接下来，分析配置数据的错误。最后，修正配置数据，如果存在错误，则重写配置数据。

67. 发明申请

US20040232942A1 Field programmable gate array and microcontroller system-on-a-chip 有权
标题翻译：现场可编程门阵列和微控制器片上系统
公开(公告)号：US20040232942A1
公开(公告)日：2004-11-25
申请号：US10821533
申请日：2004-04-08
申请人： Actel Corporation
发明人： Arunangshu Kundu , Arnold Goldfein , William C. Plants , David Hightower
IPC分类号： H03K019/177
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
摘要翻译：片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

68. 发明授权

US6160420A Programmable interconnect architecture 失效
标题翻译：可编程互连体系结构
公开(公告)号：US6160420A
公开(公告)日：2000-12-12
申请号：US754189
申请日：1996-11-12
申请人： Abbas El Gamal , Khaled A. El-Avat , Amr Mohsen
发明人： Abbas El Gamal , Khaled A. El-Avat , Amr Mohsen
IPC分类号： G01R31/28 , G01R31/3185 , H01L25/00 , H03K19/177
CPC分类号： G01R31/2884 , G01R31/318516 , G01R31/318519 , H03K19/17704 , H03K19/17736
摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.
摘要翻译：公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。在一个实施例中，矩阵中的多个逻辑单元或模块通过竖直和水平布线通道连接。接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。接线通道包括通过常开可编程连接的接线段。位于要连接的任何两个段的交点处的元素。

69. 发明授权

US6150705A Dielectric-polysilicon-dielectric-polysilicon-dielectric antifuse for field programmable logic application 失效
标题翻译：用于现场可编程逻辑应用的介质 - 多晶硅 - 介电多晶硅 - 电介质反熔丝
公开(公告)号：US6150705A
公开(公告)日：2000-11-21
申请号：US571615
申请日：1995-12-13
申请人： Wenn-Jei Chen
发明人： Wenn-Jei Chen
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S148/055
摘要： A novel antifuse structure includes a novel antifuse material layer comprises a first dielectric layer, a first polysilicon layer (which may optionally be lightly doped) disposed over the first dielectric layer, and a second dielectric layer disposed over the first polysilicon layer. The dielectric layers may be formed of silicon nitride, silicon dioxide, silicon oxynitride and combinations of the foregoing. Additional layers may also be included to form D/P/D/P/D, D/P/D/a-Si/D sandwiches, and the like. The polysilicon layer provides the ability to control the breakdown voltage of the antifuse through control of the doping level while maintaining a relatively large thickness of the antifuse material layer resulting in low capacitance for the antifuse. The antifuse material layer is compatible with high temperature processes (500.degree. C.-950.degree. C.) and may be carried out in the range of 400.degree. C.-950.degree. C. making it compatible with a wide range of processes.
摘要翻译：一种新颖的反熔丝结构包括一种新颖的反熔丝材料层，其包括第一介电层，设置在第一介电层上的第一多晶硅层（其可任选地是轻掺杂的）和设置在第一多晶硅层上的第二介电层。电介质层可以由氮化硅，二氧化硅，氮氧化硅以及前述的组合形成。还可以包括另外的层以形成D / P / D / P / D，D / P / D / a-Si / D三明治等。多晶硅层提供通过控制掺杂水平来控制反熔丝的击穿电压的能力，同时保持反熔丝材料层的相对较大的厚度，从而导致反熔丝的低电容。反熔丝材料层与高温工艺（500℃〜950℃）兼容，可在400℃〜950℃的范围内进行，使其与广泛的工艺相容。

70. 发明授权

US5952847A Multiple logic family compatible output driver 失效
标题翻译：多逻辑系列兼容输出驱动器
公开(公告)号：US5952847A
公开(公告)日：1999-09-14
申请号：US673701
申请日：1996-06-25
申请人： William C. Plants , Gregory W. Bakker
发明人： William C. Plants , Gregory W. Bakker
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018521
摘要： The output buffer circuit according to the present invention is connected to an I/O pad of the integrated circuit. The output buffer circuit includes an output totem pole, a level shifter and enable logic. The output totem pole has a first input connected to the level shifter and a second input connected to the enable logic. The output of the totem pole is connected to an I/O pad. The totem pole includes a pullup transistor connected to 3.3 volt Vcc and a pulldown transistor connected to ground. In a first embodiment of the invention, the pullup transistor in the totem pole is an N-channel MOS transistor, and in a second embodiment of the invention, the pullup transistor in the totem pole is a P-channel MOS transistor formed in an N-well tied to the 5 volt Vcc. In the first embodiment of the present invention, the N-Channel MOS pullup transistor is turned on by a 5 volt signal from the level shifter. In the second embodiment of the present invention, the P-Channel MOS pullup transistor is turned on by a ground level signal from the level shifter. The enable logic drives the output of the totem pole in response to input signals to the enable logic. The inputs to the enable logic are a Data input, a Global enable input and an Output enable input.
摘要翻译：根据本发明的输出缓冲器电路连接到集成电路的I / O焊盘。输出缓冲电路包括输出图腾柱，电平移位器和使能逻辑。输出图腾柱具有连接到电平移位器的第一输入端和连接到使能逻辑的第二输入端。图腾柱的输出连接到I / O焊盘。图腾柱包括连接到3.3伏Vcc的上拉晶体管和连接到地的下拉晶体管。在本发明的第一实施例中，图腾柱中的上拉晶体管是N沟道MOS晶体管，在本发明的第二实施例中，图腾柱中的上拉晶体管是形成在N沟道MOS晶体管中的P沟道MOS晶体管 - 连接到5伏Vcc。在本发明的第一实施例中，N沟道MOS上拉晶体管由来自电平移位器的5伏特信号导通。在本发明的第二实施例中，P沟道MOS上拉晶体管由来自电平移位器的接地电平信号导通。响应于使能逻辑的输入信号，使能逻辑驱动图腾柱的输出。使能逻辑的输入是数据输入，全局使能输入和输出使能输入。

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