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61. 发明授权

US07683657B2 Calibration circuit of on-die termination device 有权
标题翻译：管芯端接装置的校准电路
公开(公告)号：US07683657B2
公开(公告)日：2010-03-23
申请号：US12099350
申请日：2008-04-08
申请人： Ki-Ho Kim
发明人： Ki-Ho Kim
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005
摘要： A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node and a reference voltage, to generate calibration codes. The calibration unit also includes a calibration resistor unit having parallel resistors which are turned on/off in response to each of the calibration codes and connected to the calibration node, a turn-on strength of at least one of the parallel resistors being controlled by a control signal.
摘要翻译：片上终端装置的校准电路包括被配置为接收校准节点的电压和参考电压的代码生成单元，以生成校准代码。校准单元还包括校准电阻器单元，其具有响应于每个校准代码并连接到校准节点的导通/截止的并联电阻器，至少一个并联电阻器的接通强度由控制信号。

62. 发明授权

US07676711B2 Test circuit for testing command signal at package level in semiconductor device 失效
标题翻译：用于在半导体器件中封装级测试指令信号的测试电路
公开(公告)号：US07676711B2
公开(公告)日：2010-03-09
申请号：US11819566
申请日：2007-06-28
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/02 , G11C29/1201 , G11C2029/3202
摘要： A test circuit for testing a command signal at a package level in a semiconductor device includes: a logic level determining unit for determining logic levels of a plurality of command flag signals in response to a plurality of internal command signals in a test mode; a storage unit for storing the plurality of command flag signals in response to a store control signal and outputting the plurality of command flag signals in series in response to an output control signal; and an output unit for driving an output signal of the storage unit to a data pad.
摘要翻译：一种用于在半导体器件中测试封装级别的命令信号的测试电路包括：逻辑电平确定单元，用于响应于测试模式中的多个内部命令信号来确定多个命令标志信号的逻辑电平; 存储单元，用于响应于存储控制信号存储多个命令标志信号，并响应输出控制信号串联输出多个命令标志信号; 以及用于将存储单元的输出信号驱动到数据垫的输出单元。

63. 发明授权

US07660176B2 Semiconductor memory device and method for driving the same 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07660176B2
公开(公告)日：2010-02-09
申请号：US11966828
申请日：2007-12-28
申请人： Hwang Hur
发明人： Hwang Hur
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/1096 , G11C11/4094 , G11C11/4096
摘要： A semiconductor memory device includes a write driver, a first precharging unit, and a second precharging unit. The write driver loads data applied to a first data line onto a second data line. The first precharging unit precharges the second data line to a precharging voltage in response to a precharging signal. The second precharging unit overdrives the second data line to a voltage higher than the precharging voltage in response to an overdriving signal enabled for a predetermined time period during an initial precharging interval of the second data line.
摘要翻译：半导体存储器件包括写驱动器，第一预充电单元和第二预充电单元。写驱动器将应用于第一数据线的数据加载到第二数据线上。第一预充电单元响应于预充电信号将第二数据线预充电到预充电电压。第二预充电单元响应于在第二数据线的初始预充电间隔期间启用预定时间段的过驱信号，将第二数据线驱动到高于预充电电压的电压。

64. 发明授权

US07651923B2 Method for forming transistor of semiconductor device 失效
标题翻译：半导体器件晶体管形成方法
公开(公告)号：US07651923B2
公开(公告)日：2010-01-26
申请号：US11730614
申请日：2007-04-03
申请人： Young Man Cho , Seung Wan Kim
发明人： Young Man Cho , Seung Wan Kim
IPC分类号： H01L21/76
CPC分类号： H01L29/1037 , H01L21/28123 , H01L21/31053 , H01L21/76224 , H01L29/66621
摘要： A method for forming a transistor of a semiconductor device, includes forming a trench by etching a semiconductor substrate on which a pad oxide film and a pad nitride film are sequentially formed; forming a isolation oxide film by filling the trench with oxide; removing an upper portion of the isolation oxide film until an upper lateral portion of the semiconductor substrate is exposed; forming a barrier nitride film over the isolation oxide film, the semiconductor substrate, and the pad nitride film; forming a sacrificial oxide film over the barrier nitride film; performing a planarization process until the pad nitride film is exposed; performing a wet etching process until the active region is exposed; forming a photoresist pattern over the active region and the barrier nitride film; and performing a dry etching process by using the photoresist pattern as an etching mask, thereby forming a recessed gate trench.
摘要翻译：一种用于形成半导体器件的晶体管的方法，包括通过蚀刻半导体衬底来形成沟槽，半导体衬底上依次形成衬垫氧化物膜和衬垫氮化物膜; 通过用氧化物填充沟槽来形成隔离氧化膜; 去除隔离氧化膜的上部直到半导体衬底的上侧部分露出; 在隔离氧化膜，半导体衬底和衬垫氮化物膜上形成阻挡氮化物膜; 在阻挡氮化物膜上形成牺牲氧化膜; 进行平坦化处理直到衬垫氮化物膜露出为止; 执行湿式蚀刻工艺，直到有源区域暴露; 在有源区和阻挡氮化物膜上形成光致抗蚀剂图案; 并通过使用光致抗蚀剂图案作为蚀刻掩模进行干蚀刻处理，从而形成凹陷栅沟槽。

65. 发明授权

US07649801B2 Semiconductor memory apparatus having column decoder for low power consumption 有权
标题翻译：具有低功耗的列解码器的半导体存储装置
公开(公告)号：US07649801B2
公开(公告)日：2010-01-19
申请号：US11716635
申请日：2007-03-12
申请人： Sang-Kwon Lee
发明人： Sang-Kwon Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C11/4074 , G11C11/4087 , G11C2207/2227
摘要： The present invention relates to a column decoder for low power consumption in a semiconductor memory apparatus. The semiconductor device according to the present invention includes a column select signal decoder, which has a driving voltage input node and uses a driving voltage, for producing a plurality of column select signals by decoding a column select control signal; and a driving voltage supply controller for controlling a supply of the driving voltage to the driving voltage input node.
摘要翻译：本发明涉及在半导体存储装置中低功耗的列解码器。根据本发明的半导体器件包括具有驱动电压输入节点并使用驱动电压的列选择信号解码器，用于通过对列选择控制信号进行解码来产生多个列选择信号; 以及用于控制对驱动电压输入节点的驱动电压的供给的驱动电压供给控制器。

66. 发明授权

US07646652B2 Internal voltage generator for use in semiconductor memory device 有权
标题翻译：用于半导体存储器件的内部电压发生器
公开(公告)号：US07646652B2
公开(公告)日：2010-01-12
申请号：US11647401
申请日：2006-12-29
申请人： Sang-Jin Byeon
发明人： Sang-Jin Byeon
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： An internal voltage generator stably supplies an internal voltage in a semiconductor device. The internal voltage generator includes: a first internal voltage generating means for supplying a first internal voltage which has a level corresponding to a first reference voltage using an external voltage; a second internal voltage generating means for supplying a second internal voltage which has a level corresponding to a second reference voltage using the external voltage; and a third internal voltage generating means for supplying a third internal voltage which has a level corresponding to a third reference voltage generated based on the first internal voltage, using the second internal voltage as a power source.
摘要翻译：内部电压发生器稳定地提供半导体器件中的内部电压。内部电压发生器包括：第一内部电压产生装置，用于使用外部电压提供具有对应于第一参考电压的电平的第一内部电压; 第二内部电压产生装置，用于使用外部电压提供具有对应于第二参考电压的电平的第二内部电压; 以及第三内部电压产生装置，用于使用第二内部电压作为电源来提供具有与基于第一内部电压产生的第三参考电压相对应的电平的第三内部电压。

67. 发明授权

US07639550B2 Semiconductor memory device with bi-directional read and write data transport 失效
标题翻译：具有双向读写数据传输的半导体存储器件
公开(公告)号：US07639550B2
公开(公告)日：2009-12-29
申请号：US11819821
申请日：2007-06-29
申请人： Sung-Joo Ha
发明人： Sung-Joo Ha
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C11/4096
摘要： A semiconductor memory device includes a pair of local input/output (IO) lines, a global IO line, a local driver configured to pull up/down voltage levels of the first and second local IO lines in response to input data, a global driver configured to pull up/down a voltage level of the global IO line in response to input data, and a data IO control block configured to transport output data from the local IO lines to the global driver and input data from the global IO line to the local driver.
摘要翻译：半导体存储器件包括一对局部输入/输出（IO）线，全局IO线，配置为响应于输入数据上拉/下降第一和第二本地IO线的电压电平的本地驱动器，全局驱动器配置为响应于输入数据上拉/下降全局IO线的电压电平，以及数据IO控制块，被配置为将输出数据从本地IO线传输到全局驱动器，并将数据从全局IO线输入到本地司机。

68. 发明授权

US07630262B2 One-transistor type dram 失效
标题翻译：单晶体管式
公开(公告)号：US07630262B2
公开(公告)日：2009-12-08
申请号：US12003923
申请日：2008-01-03
申请人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
发明人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
IPC分类号： G11C7/02
CPC分类号： G11C11/404 , G11C11/4091 , G11C11/4096 , G11C11/4099 , G11C2211/4016
摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.
摘要翻译：单晶体管型DRAM包括连接在位线和源极线之间并由字线控制的浮体存储元件。 DRAM包括沿行方向布置的多个源极线和字线，沿列方向布置的多个位线，沿列方向布置的多个参考位线，包括浮体存储元件的单元阵列和形成在源极线，字线和位线交叉的区域中，形成在源极线，字线和位线交叉配置的区域中的包括浮体存储元件的基准单元阵列输出具有多个电平的参考电流;多个参考电压产生单元，连接到参考位线并被配置为产生与具有多个电平的参考电流相对应的多个参考电压;以及读出放大器和写入驱动单元连接到位线并被配置为接收多个参考电压。

69. 发明授权

US07629822B2 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
标题翻译：半导体存储器件中的延迟锁定环和其中产生分频时钟的方法
公开(公告)号：US07629822B2
公开(公告)日：2009-12-08
申请号：US12078095
申请日：2008-03-27
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.
摘要翻译：提供了一种延迟锁定环（DLL）和用于在其中产生分频时钟的方法。在DLL中，用于相位比较的参考频率的宽度可以根据工作频率的大小而改变。在DLL中，时钟缓冲器接收等于外部时钟的时钟并产生内部时钟。使能时钟发生器使用为执行预定义的操作生成的命令信号生成1周期使能时钟或2周期使能时钟。根据从外部输入的地址指令信号生成指令信号。时钟分频器分隔内部时钟以产生分频时钟。分频时钟由1周期使能时钟或2周期使能时钟控制，使得分频时钟为1周期分频时钟或2周期分频时钟。

70. 发明授权

US07629821B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07629821B2
公开(公告)日：2009-12-08
申请号：US11987834
申请日：2007-12-05
申请人： Seok-Bo Shim
发明人： Seok-Bo Shim
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/0818
摘要： A semiconductor memory device includes a phase comparator, a delay chain, a delay controller, a fine delay chain, a delay model, a locking state detector, and a fine delay controller. The phase comparator compares a phase of a reference clock with that of a feedback clock. The delay chain delays and outputs the reference clock. The delay controller controls a delay value of the delay chain in response to the comparison result of the phase comparator. The fine delay chain outputs a delay value of a clock outputted from the delay chain. The delay model delays a clock to a modeled delay value to provide a delayed clock as the feedback clock. The locking state detector generates a locking variation signal corresponding to a phase difference between the reference clock and the feedback clock. The fine delay controller controls a fine adjustment value of the fine delay chain.
摘要翻译：半导体存储器件包括相位比较器，延迟链，延迟控制器，精细延迟链，延迟模型，锁定状态检测器和精细延迟控制器。相位比较器将参考时钟的相位与反馈时钟的相位进行比较。延迟链延迟并输出参考时钟。响应于相位比较器的比较结果，延迟控制器控制延迟链的延迟值。精细延迟链输出从延迟链输出的时钟的延迟值。延迟模型将时钟延迟到建模延迟值，以提供延迟时钟作为反馈时钟。锁定状态检测器产生对应于参考时钟和反馈时钟之间的相位差的锁定变化信号。精细延迟控制器控制精细延迟链的精细调整值。

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