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61. 发明授权

US07687861B2 Silicided regions for NMOS and PMOS devices 有权
标题翻译：用于NMOS和PMOS器件的硅化区域
公开(公告)号：US07687861B2
公开(公告)日：2010-03-30
申请号：US11248555
申请日：2005-10-12
申请人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
发明人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
IPC分类号： H01L27/092
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.
摘要翻译：提供了一种其上形成有NMOS和PMOS器件的半导体器件。 NMOS器件具有在栅电极旁边形成的附加间隔物，以允许硅化物区域远离栅电极形成。通过将硅化物区域放置在更远离栅电极的位置，减少了间隔物下方的硅化物区域的横向侵蚀的影响，特别是泄漏。形成半导体器件的方法可以包括在PMOS和NMOS器件的栅电极旁边形成多个间隔物，并且可以执行一个或多个注入以将杂质注入到PMOS和NMOS器件的源极/漏极区域中。可以选择性地去除与PMOS器件的栅电极旁边的一个或多个间隔物。此后，源极/漏极区域可以被硅化。

62. 发明授权

US07625801B2 Silicide formation with a pre-amorphous implant 有权
标题翻译：具有预非晶态植入物的硅化物形成
公开(公告)号：US07625801B2
公开(公告)日：2009-12-01
申请号：US11523678
申请日：2006-09-19
申请人： Chii-Ming Wu , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2658 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal layer on the silicon-containing compound stressor while the upper portion of the SiGe stressor is amorphous, and annealing to react the metal layer with the silicon-containing compound stressor to form a silicide region. The silicon-containing compound stressor includes SiGe or SiC.
摘要翻译：一种用于形成半导体结构的方法包括：提供半导体衬底，在半导体衬底上形成栅极叠层，在栅堆叠附近形成含硅化合物应力源，将非硅化离子注入到含硅化合物应力器中以使上层含硅化合物应激源的部分，在含硅化合物应激物上形成金属层，同时SiGe应力源的上部是无定形的，退火使金属层与含硅化合物应激反应物形成硅化物区域。含硅化合物应激源包括SiGe或SiC。

63. 发明授权

US07429333B2 Method for fabricating microneedle array and method for fabricating embossing mold of microneedle array 有权
标题翻译：微针阵列的制造方法和微针阵列压花模具的制造方法
公开(公告)号：US07429333B2
公开(公告)日：2008-09-30
申请号：US11691573
申请日：2007-03-27
申请人： Jin-Chern Chiou , Chen-Chun Hung , Chih-Wei Chang
发明人： Jin-Chern Chiou , Chen-Chun Hung , Chih-Wei Chang
IPC分类号： B44C1/22 , C25F3/00
CPC分类号： B29C33/40 , B29C33/3878
摘要： The present invention discloses a method for fast fabricating microneedle arrays with an embossing process and a method for fabricating an embossing mold of a microneedle array, wherein a master pattern of a high aspect ratio silicon microneedle array is fabricated with a microelectromechanical technology, and the master pattern is used to fabricate an embossing mold; a thermosetting material is filled into the embossing mold; then, baking, pressing and mold-stripping are undertaken; thereby, disposable solid polymer microneedle arrays can be batch-fabricated.
摘要翻译：本发明公开了一种用压花工艺快速制造微针阵列的方法和一种用于制造微针阵列的压花模具的方法，其中利用微机电技术制造高纵横比硅微针阵列的母模，图案用于制造压花模具; 将热固性材料填充到压花模具中; 然后进行烘烤，压制和脱模; 从而可以批量制造一次性固体聚合物微针阵列。

64. 发明申请

US20080122071A1 Heat dissipating semiconductor package and fabrication method therefor 审中-公开
标题翻译：散热半导体封装及其制造方法
公开(公告)号：US20080122071A1
公开(公告)日：2008-05-29
申请号：US11986362
申请日：2007-11-21
申请人： Wen-Tsung Tseng , Ho-Yi Tsai , Chien-Ping Huang , Chih-Wei Chang , Cheng-Hsu Hsiao
发明人： Wen-Tsung Tseng , Ho-Yi Tsai , Chien-Ping Huang , Chih-Wei Chang , Cheng-Hsu Hsiao
IPC分类号： H01L23/373
CPC分类号： H01L23/3128 , H01L21/568 , H01L23/4334 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/15311
摘要： A heat dissipating semiconductor package and the fabrication method therefor are provided. The fabrication method for the heat dissipating semiconductor package mainly includes steps of: containing a substrate having a chip mounted thereon in an aperture of a carrier, wherein the carrier has an electroconductive layer; allowing a heat dissipating structure having supporting portions to be mounted on and electrically connected to the electroconductive layer of the carrier via the supporting portions thereof while heat dissipating structure being mounted on the chip; after an encapsulation process and removing a part of the encapsulant above the heat dissipating sheet by lapping to expose a surface of the heat dissipating structure from the encapsulant, depositing and forming a metal passivation layer on the surface of the heat dissipating structure by electroplating for preventing the heat dissipating structure from oxidizing.
摘要翻译：提供一种散热半导体封装及其制造方法。用于散热半导体封装的制造方法主要包括以下步骤：在载体的孔中容纳其上安装有芯片的基板，其中载体具有导电层; 允许散热结构，其具有支撑部分，其安装在载体的导电层上并通过其支撑部分电连接，同时散热结构安装在芯片上; 在封装工艺之后并且通过研磨去除散热片上方的一部分密封剂，以从密封剂暴露出散热结构的表面，在散热结构的表面上沉积和形成金属钝化层，通过电镀防止散热结构从氧化。

65. 发明申请

US20080083957A1 MICRO-ELECTROMECHANICAL SYSTEM PACKAGE 审中-公开
标题翻译：微电子系统包装
公开(公告)号：US20080083957A1
公开(公告)日：2008-04-10
申请号：US11539025
申请日：2006-10-05
申请人： Wen-Chieh Wei , Hong-Ching Her , Shih-Chin Gong , Chih-Wei Chang
发明人： Wen-Chieh Wei , Hong-Ching Her , Shih-Chin Gong , Chih-Wei Chang
IPC分类号： H01L29/84
CPC分类号： H04R19/005 , B81B7/0064 , B81B2201/0257 , B81B2207/012 , H01L2224/48137 , H01L2224/73265 , H01L2224/97 , H01L2924/15151 , H01L2924/16235 , H01L2924/181 , H01L2924/19105 , H01L2924/3025 , H04R19/04 , H01L2924/00 , H01L2924/00012
摘要： A micro-electromechanical system package includes a substrate, a group of components, isolative stuff and a conductive shield. The substrate is made with an upper face and a lower face. The group is mounted on the upper face of the substrate. The isolative stuff seals the group and the upper face of the substrate, thus protecting the group from moisture. The conductive shield covers the isolative stuff, thus protecting the group from electromagnetic interference.
摘要翻译：微机电系统封装包括基板，一组部件，隔离材料和导电屏蔽。基板由上表面和下表面制成。该组安装在基板的上表面上。隔离物密封基体的基团和上表面，从而保护基团免受潮湿。导电屏蔽覆盖隔离材料，从而保护组免受电磁干扰。

66. 发明申请

US20080009763A1 Microprobe array structure and method for manufacturing the same 有权
标题翻译：微阵列阵列结构及其制造方法
公开(公告)号：US20080009763A1
公开(公告)日：2008-01-10
申请号：US11599303
申请日：2006-11-15
申请人： Jin-Chern Chiou , Chih-Wei Chang , Chen-Chun Hung
发明人： Jin-Chern Chiou , Chih-Wei Chang , Chen-Chun Hung
IPC分类号： A61B5/04
CPC分类号： A61B5/0408 , A61B5/0478 , A61B5/14514 , A61B5/685
摘要： A microprobe array structure with self-stabilization capability and a method for manufacturing the same are proposed. The microprobe array structure is used to sense various biopotential signals, and is characterized in that the etching parameters are controlled during etching to manufacture a microprobe structure with a reduced bottom cross section so that the microprobe can be firmly stabilized in the skin tissue. Moreover, a conducting layer is formed on the microprobe to sense signals. A design of electric isolation between microprobes is also proposed. The microprobe array can therefore be used for the measurement of various biopotential signals, and can also be used as a stimulus.
摘要翻译：提出了具有自稳定能力的微探针阵列结构及其制造方法。微探针阵列结构用于感测各种生物电位信号，其特征在于在蚀刻期间控制蚀刻参数以制造具有减小的底部横截面的微探针结构，使得微探针能够牢固地稳定在皮肤组织中。此外，在微探针上形成导电层以感测信号。还提出了微型笔之间的电隔离设计。因此，微探针阵列可以用于各种生物电位信号的测量，并且也可以用作刺激。

67. 发明申请

US20070290325A1 Surface mounting structure and packaging method thereof 审中-公开
标题翻译：表面安装结构及其包装方法
公开(公告)号：US20070290325A1
公开(公告)日：2007-12-20
申请号：US11453803
申请日：2006-06-16
申请人： Kuo-Liang Wu , Kuo-Shu Iu , Chih-Wei Chang
发明人： Kuo-Liang Wu , Kuo-Shu Iu , Chih-Wei Chang
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L23/49562 , H01L24/01 , H01L24/80 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , H01L2924/14
摘要： A surface mounting structure and a packaging method thereof comprises a chip, a first conducting wire and a second conducting wire. The two conducting wires instead of lead frame architecture of the prior art is that the lead frame and a bridge jumper connected with N junction and P junction instead of the two conducting wires. The two conducting wires are drawn out from a bottom of a package, and are pressed and bent to original surface of the surface mounting pins so as to increase space utilization rate. Thereby it is to improve a complicated lead frame architecture of the prior art, increase use space and simplify system design.
摘要翻译：表面安装结构及其包装方法包括芯片，第一导线和第二导线。两个导线代替现有技术的引线框结构是引线框架和桥接跳线与N结和P结连接而不是两条导线。两根导线从封装的底部拉出，并被按压并弯曲到表面安装销的原始表面，以提高空间利用率。因此，改进现有技术的复杂引线框结构，增加使用空间并简化系统设计。

68. 发明授权

US07256137B2 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US07256137B2
公开(公告)日：2007-08-14
申请号：US11052938
申请日：2005-02-07
申请人： Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue , Ju-Wang Hsu , Ming-Huan Tsai
发明人： Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue , Ju-Wang Hsu , Ming-Huan Tsai
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

69. 发明授权

US07205234B2 Method of forming metal silicide 有权
标题翻译：形成金属硅化物的方法
公开(公告)号：US07205234B2
公开(公告)日：2007-04-17
申请号：US10772938
申请日：2004-02-05
申请人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/44
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method of optimizing the formation of nickel silicide on regions of a MOSFET structure, has been developed. The method features formation of nickel silicide using an anneal procedure performed at a temperature below which nickel silicide instability and agglomeration occurs. A thin titanium interlayer is first formed on the MOSFET structure prior to nickel deposition, allowing an anneal procedure, performed after nickel deposition, to successfully form nickel silicide at a temperature of about 400° C. To obtain the desired conformality and thickness uniformity the thin titanium interlayer is formed via an atomic layer deposition procedure.
摘要翻译：已经开发了在MOSFET结构的区域上优化硅化镍的形成的方法。该方法的特征是使用在低于该温度的镍硅化物不稳定性和聚集发生的温度下进行的退火程序形成硅化镍。首先在镍沉积之前在MOSFET结构上形成薄的钛中间层，允许在镍沉积之后进行的退火程序在约400℃的温度下成功形成硅化镍。为了获得所需的共形性和厚度均匀性，薄的通过原子层沉积工艺形成钛夹层。

70. 发明授权

US07183413B2 Aminoquinoline compounds 失效
标题翻译：氨基喹啉化合物
公开(公告)号：US07183413B2
公开(公告)日：2007-02-27
申请号：US10819646
申请日：2004-04-06
申请人： Chu-Chung Lin , Jen-Fuh Liu , Chih-Wei Chang , Shu-Jen Chen , Yibin Xiang , Pei-Chin Cheng , Jiing-Jyh Jan
发明人： Chu-Chung Lin , Jen-Fuh Liu , Chih-Wei Chang , Shu-Jen Chen , Yibin Xiang , Pei-Chin Cheng , Jiing-Jyh Jan
IPC分类号： C07D215/16 , C07D215/38
CPC分类号： C07D401/14 , A61K31/4745 , A61K31/519 , C07D215/42 , C07D215/44 , C07D215/46 , C07D219/12 , C07D221/16 , C07D401/12 , C07D409/14 , C07D413/14 , C07D417/12 , C07D417/14 , C07D471/04
摘要： This invention relates to treating inflammatory and immune diseases with certain aminoquinoline compounds that bind to CXCR3 receptors. The aminoquinoline compounds are covered by the formula (I) shown below. Each variable is defined in the specification.
摘要翻译：本发明涉及用与CXCR3受体结合的某些氨基喹啉化合物治疗炎症和免疫疾病。氨基喹啉化合物被下面所示的式（I）覆盖。每个变量在规范中定义。

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