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    • 61. 发明授权
    • Cache which provides partial tags from non-predicted ways to direct search if way prediction misses
    • 从非预测方式提供部分标签的缓存,如果方式预测错失,则直接搜索
    • US06687789B1
    • 2004-02-03
    • US09476577
    • 2000-01-03
    • James B. KellerKeith R. SchakelPuneet Sharma
    • James B. KellerKeith R. SchakelPuneet Sharma
    • G06F1200
    • G06F12/0864G06F9/30149G06F9/3824G06F9/3832G06F9/3836G06F9/3838G06F9/384G06F9/3857G06F2212/6082Y02D10/13
    • A cache is coupled to receive an input address and a corresponding way prediction. The cache provides output bytes in response to the predicted way (instead of, performing tag comparisons to select the output bytes). Furthermore, a tag may be read from the predicted way and only partial tags are read from the non-predicted ways. The tag is compared to the tag portion of the input address, and the partial tags are compared to a corresponding partial tag portion of the input address. If the tag matches the tag portion of the input address, a hit in the predicted way is detected and the bytes provided in response to the predicted way are correct. If the tag does not match the tag portion of the input address, a miss in the predicted way is detected. If none of the partial tags match the corresponding partial tag portion of the input address, a miss in the cache is determined. On the other hand, if one or more of the partial tags match the corresponding partial tags portion of the input address, the cache searches the corresponding ways to determine whether or not the input address hits or misses in the cache.
    • 高速缓存被耦合以接收输入地址和相应的方式预测。 缓存提供响应于预测方式的输出字节(而不是执行标签比较以选择输出字节)。 此外,可以从预测的方式读取标签,并且仅从非预测方式读取部分标签。 将标签与输入地址的标签部分进行比较,并将部分标签与输入地址的相应部分标签部分进行比较。 如果标签与输入地址的标签部分匹配,则以预测的方式检测到命中,并且响应于预测方式提供的字节是正确的。 如果标签与输入地址的标签部分不匹配,则以预测的方式检测到未命中。 如果部分标签中没有一个与输入地址的相应部分标签部分匹配,则确定高速缓存中的未命中。 另一方面,如果一个或多个部分标签与输入地址的相应部分标签部分匹配,则高速缓存搜索相应的方式以确定输入地址是否在高速缓存中命中或丢失。
    • 62. 发明授权
    • Line predictor entry with location pointers and control information for corresponding instructions in a cache line
    • 具有位置指针的行预测值条目和缓存行中对应指令的控制信息
    • US06546478B1
    • 2003-04-08
    • US09418098
    • 1999-10-14
    • James B. KellerPuneet SharmaKeith R. SchakelFrancis M. Matus
    • James B. KellerPuneet SharmaKeith R. SchakelFrancis M. Matus
    • G06F938
    • G06F9/3816G06F9/30149G06F9/322G06F9/3804G06F9/384
    • A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The alignment information may be, for example, instruction pointers, each of which directly locates a corresponding instruction within a plurality of instruction bytes fetched in response to the fetch address. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Furthermore, each entry may store additional information regarding the terminating instruction within the entry. In one embodiment, the additional information includes an indication of the branch displacement when the terminating instruction is a branch instruction. In another embodiment, the additional information includes the entry point for a microcode instruction when the terminating instruction is a microcode instruction. Furthermore, the microcode instruction may be identified by an instruction pointer corresponding to a particular decode unit which is coupled to the microcode unit.
    • 行预测器缓存对齐信息的指令。 响应于每个提取地址,行预测器提供从取指址开始的指令的对齐信息,以及该指令之后的一个或多个附加指令。 对准信息可以是例如指令指针,每个指令指针直接定位响应于取出地址取出的多个指令字节中的对应指令。 线预测器可以包括具有多个条目的存储器,每个条目存储多达预定义的最大数量的指令指针以及与由指令指针中的第一个标识的指令相对应的读取地址。 此外,每个条目可以存储关于条目内的终止指令的附加信息。 在一个实施例中,附加信息包括当终止指令是分支指令时分支位移的指示。 在另一个实施例中,当终止指令是微码指令时,附加信息包括微代码指令的入口点。 此外,微代码指令可以由对应于耦合到微代码单元的特定解码单元的指令指针来识别。
    • 63. 发明授权
    • Pipeline elements which verify predecode information
    • 验证预解码信息的管道元素
    • US06502185B1
    • 2002-12-31
    • US09476936
    • 2000-01-03
    • James B. KellerPuneet SharmaKeith R. SchakelFrancis M. Matus
    • James B. KellerPuneet SharmaKeith R. SchakelFrancis M. Matus
    • G06F930
    • G06F9/382G06F9/30152G06F9/30174G06F9/322G06F9/3806G06F9/3816G06F9/3861
    • A processor includes an instruction cache and a predecode cache which is not actively maintained coherent with the instruction cache. The processor fetches instruction bytes from the instruction cache and predecode information from the predecode cache. Instructions are provided to a plurality of decode units based on the predecode information, and the decode units decode the instructions and verify that the predecode information corresponds to the instructions. More particularly, each decode unit may verify that a valid instruction was decoded, and that the instruction succeeds a preceding instruction decoded by another decode unit. Additionally, other units involved in the instruction processing pipeline stages prior to decode may verify portions of the predecode information. If the predecode information does not correspond to the fetched instructions, the predecode information may be corrected (either by predecoding the instruction bytes or by updating the predecode information, if the update may be determined without predecoding the instruction bytes). In one particular embodiment, the predecode cache may be a line predictor which stores instruction pointers indexed by a portion of the fetch address. The line predictor may thus experience address aliasing, and predecode information may therefore not correspond to the instruction bytes. However, power may be conserved by not storing and comparing the entire fetch address.
    • 处理器包括指令高速缓存和未被主动地保持与指令高速缓存相关联的预解码高速缓存。 处理器从指令高速缓存中获取指令字节,并从预代码高速缓存预先解码信息。 基于预解码信息向多个解码单元提供指令,并且解码单元解码指令并验证预解码信息对应于指令。 更具体地,每个解码单元可以验证有效指令被解码,并且该指令成功接收由另一解码单元解码的先前指令。 此外,涉及在解码之前的指令处理流水线阶段的其他单元可以验证预解码信息的部分。 如果预解码信息不对应于获取的指令,则可以通过预编码指令字节或通过更新预解码信息来校正预解码信息,如果可以在不预编译指令字节的情况下确定更新的话)。 在一个特定实施例中,预解码高速缓存可以是存储由获取地址的一部分索引的指令指针的行预测器。 因此,线预测器可能会遇到地址混叠,因此预解码信息可能不对应于指令字节。 然而,通过不存储和比较整个读取地址可以节省功率。
    • 69. 发明授权
    • Integrated circuit with degradation monitoring
    • 具有降级监控的集成电路
    • US09329229B2
    • 2016-05-03
    • US13956126
    • 2013-07-31
    • Magdy S AbadirPuneet Sharma
    • Magdy S AbadirPuneet Sharma
    • H03M13/11G01R31/28G01R31/317H03K3/037
    • G01R31/2882G01R31/31725H03K3/0375
    • An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
    • 一种包括劣化监测电路的集成电路。 劣化监视电路包括具有可编程延迟元件的比较电路,该可编程延迟元件包括耦合到定时路径的数据节点的输入,并且具有输出以提供延迟可编程量的数据节点的数据信号的延迟信号。 比较电路包括逻辑比较器,其提供数据节点的数据信号和延迟元件的输出之间的逻辑比较。 监视电路包括采样电路,该采样电路提供对于时钟信号线的时钟信号采样的逻辑比较器的输出的采样信号。 监视电路包括保持电路,该保持电路提供指示在时钟信号线的时钟信号的边沿转换的预定时间内数据节点的数据信号的信号。