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61. 发明授权

US07023272B2 Multi-band low noise amplifier system 有权
标题翻译：多频段低噪声放大器系统
公开(公告)号：US07023272B2
公开(公告)日：2006-04-04
申请号：US10827577
申请日：2004-04-19
申请人： Chih-Ming Hung , Dirk Leipold , Yo-Chuol Ho
发明人： Chih-Ming Hung , Dirk Leipold , Yo-Chuol Ho
IPC分类号： H03F3/68
CPC分类号： H03F3/45179 , H03F1/223 , H03F1/565 , H03F3/193 , H03F2200/294 , H03F2200/372 , H03F2200/492 , H03F2203/45394 , H03F2203/7209
摘要： A low noise amplifier (LNA) operates over multiple frequency bands while occupying less silicon area than known LNA implementations. The LNA includes output matching that can be tuned by an adjustable inductor together with a tunable capacitor bank.
摘要翻译：低噪声放大器（LNA）在多个频带上工作，而占用比已知LNA实现更少的硅面积。 LNA包括可调谐电感器和可调电容器组一起调谐的输出匹配。

62. 发明授权

US06959049B2 Multi-tap, digital-pulse-driven mixer 有权
标题翻译：多抽头，数字脉冲驱动搅拌机
公开(公告)号：US06959049B2
公开(公告)日：2005-10-25
申请号：US09828338
申请日：2001-04-06
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D7/00 , H03D7/12 , H03D7/14 , H04B1/26 , H04B1/28 , H03K9/00 , H04B1/16 , H04L27/08
CPC分类号： H03D7/1441 , H03D7/125 , H03D7/1466 , H03D7/1475 , H04B1/28
摘要： A multi-tap, digital-pulse-driven mixer advantageously avoids local oscillator (11) leakage by shifting the local oscillator frequency (FLO) out of the received frequency band. Low noise figures are advantageously realized by the use of digital pulses (51, 52) as mixer drive signals (16).
摘要翻译：多抽头数字脉冲驱动混频器有利地通过将本地振荡器频率（F LO LO）从接收频带中移位来避免本地振荡器（11）的泄漏。通过使用数字脉冲（51,52）作为混频器驱动信号（16），有利地实现了低噪声系数。

63. 发明申请

US20050195917A1 Method and apparatus for crystal drift compensation 审中-公开
标题翻译：晶体漂移补偿方法和装置
公开(公告)号：US20050195917A1
公开(公告)日：2005-09-08
申请号：US10883501
申请日：2004-06-30
申请人： Robert Staszewski , Dirk Leipold
发明人： Robert Staszewski , Dirk Leipold
IPC分类号： H04L27/04
CPC分类号： H03J7/047 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L1/00 , H03L2207/50
摘要： A mobile device includes frequency synthesizer circuitry for generating a channel frequency at a multiple of a reference frequency. The reference frequency is generated by a free-running crystal oscillator, without frequency stabilization circuitry. Variations in the output of the crystal oscillator are compensated by adjusting the multiplication factor of the frequency synthesizer.
摘要翻译：移动设备包括用于以参考频率的倍数产生频道频率的频率合成器电路。参考频率由自由运行的晶体振荡器产生，没有频率稳定电路。通过调整频率合成器的乘法因子来补偿晶体振荡器输出的变化。

64. 发明授权

US06882829B2 Integrated circuit incorporating RF antenna switch and power amplifier 有权
标题翻译：集成电路结合RF天线开关和功率放大器
公开(公告)号：US06882829B2
公开(公告)日：2005-04-19
申请号：US10114227
申请日：2002-04-02
申请人： Alexander Mostov , Dirk Leipold
发明人： Alexander Mostov , Dirk Leipold
IPC分类号： H04B1/04 , H04B1/48 , H04B1/44
CPC分类号： H04B1/48 , H04B1/04
摘要： A novel integrated circuit incorporating a transmit/receive antenna switch capable of being integrated using silicon based RF CMOS semiconductor processes and a power amplifier on the same substrate. The switch circuit is constructed whereby the substrate (i.e. bulk) terminals of the FETs are left floating thus improving the isolation and reducing the insertion loss of the switch. Floating the substrate of the transistors eliminates most of the losses caused by leakage paths through parasitic capacitances internal to the transistor thus improving the isolation and reducing the insertion loss of the switch. Alternatively, the substrate can be connected to the source or to ground via a resistor of sufficiently high value to effectively float the substrate.
摘要翻译：一种新颖的集成电路，其结合了能够使用硅基RF CMOS半导体工艺集成的发射/接收天线开关和在同一衬底上的功率放大器。开关电路被构造成使得FET的衬底（即本体）端子悬空，从而改善隔离并降低开关的插入损耗。浮置晶体管的基板消除了由通过晶体管内部的寄生电容的泄漏路径引起的大部分损耗，从而改善了隔离并降低了开关的插入损耗。或者，衬底可以通过足够高的电阻器连接到源极或接地，以有效地浮动衬底。

65. 发明授权

US06429693B1 Digital fractional phase detector 有权
$Digital fractional phase detector$
标题翻译：数字分数相位检测器
公开(公告)号：US06429693B1
公开(公告)日：2002-08-06
申请号：US09608317
申请日：2000-06-30
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D324
CPC分类号： H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/50
摘要： A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.
摘要翻译：提供数字分数相位检测器以实现频率合成器架构，其自然地将发射机调制能力与宽带全数字PLL调制方案相结合，以通过在同步相域中操作来最大化数字密集型实现。通过实施与参考计算相关联的定时调整，跨数字控制VCO提供同步逻辑，并且与VCO输出时钟同步，以允许频率控制字包含信道信息和发送调制信息。数字分数相位检测器能够容纳量化方案，以通过使用时间 - 数字转换器来测量VCO输出时钟的显着边缘与参考时钟之间的分数延迟差，以将时差表示为要使用的数字字由频率合成器。

66. 发明授权

US08855236B2 Digital amplitude modulation 有权
标题翻译：数字幅度调制
公开(公告)号：US08855236B2
公开(公告)日：2014-10-07
申请号：US13237740
申请日：2011-09-20
申请人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
发明人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
IPC分类号： H03C1/52 , H04L27/36
CPC分类号： H04L27/361
摘要： A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.
摘要翻译：使用正交调制的发射机包括用于将数据符号转换成极性形式的矩形到极化转换器，其中每个极性符号具有幅度信号和角度信号。数字相位调制电路包括全数字PLL电路，用于响应角度信号频率控制字（FCW）和载波频率FCW产生相位调制的RF载波信号。用于放大相位调制信号的数字控制放大器由数字幅度控制电路控制，用于响应于幅度信号来控制数字控制放大器的增益。

67. 发明申请

US20090207940A1 Predistortion Calibration In A Transceiver Assembly 审中-公开
标题翻译：收发器组件中的预失真校准
公开(公告)号：US20090207940A1
公开(公告)日：2009-08-20
申请号：US12432447
申请日：2009-04-29
申请人： Robert Bogdan Staszewski , Dirk Leipold
发明人： Robert Bogdan Staszewski , Dirk Leipold
IPC分类号： H04L25/03 , H04L25/49
CPC分类号： H03F1/3282 , H03F1/0211 , H03F1/3247 , H03F2200/331
摘要： Systems and methods are provided for calibrating a digital predistorter in an integrated transceiver circuit. A digital transmitter path provides a signal from a digital input. The transmitter path includes a digital predistorter that predistorts the digital input to mitigate nonlinearities associated with a power amplifier. The integrated transceiver circuit further includes a receiver path associated with the digital transmitter path. A coupling element provides the signal from the transmitter path to the receiver path. A signal evaluator determines values for at least one parameter associated with the digital predistorter based on the signal.
摘要翻译：提供了用于校准集成收发器电路中的数字预失真器的系统和方法。数字发射器路径提供来自数字输入的信号。发射机路径包括数字预失真器，其预失真数字输入以减轻与功率放大器相关联的非线性。集成收发器电路还包括与数字发送器路径相关联的接收器路径。耦合元件提供从发射机路径到接收机路径的信号。信号评估器基于该信号确定与数字预失真器相关联的至少一个参数的值。

68. 发明授权

US07555057B2 Predistortion calibration in a transceiver assembly 有权
标题翻译：收发器组件中的预失真校准
公开(公告)号：US07555057B2
公开(公告)日：2009-06-30
申请号：US10749654
申请日：2003-12-31
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H04K1/02 , H04L25/03 , H04L25/49
CPC分类号： H03F1/3282 , H03F1/0211 , H03F1/3247 , H03F2200/331
摘要： Systems and methods are provided for calibrating a digital predistorter in an integrated transceiver circuit. A digital transmitter path provides a signal from a digital input. The transmitter path includes a digital predistorter that predistorts the digital input to mitigate nonlinearities associated with a power amplifier. The integrated transceiver circuit further includes a receiver path associated with the digital transmitter path. A coupling element provides the signal from the transmitter path to the receiver path. A signal evaluator determines values for at least one parameter associated with the digital predistorter based on the signal.
摘要翻译：提供了用于校准集成收发器电路中的数字预失真器的系统和方法。数字发射器路径提供来自数字输入的信号。发射机路径包括数字预失真器，其预失真数字输入以减轻与功率放大器相关联的非线性。集成收发器电路还包括与数字发送器路径相关联的接收器路径。耦合元件提供从发射机路径到接收机路径的信号。信号评估器基于该信号确定与数字预失真器相关联的至少一个参数的值。

69. 发明申请

US20090096525A1 Power amplifier 有权
标题翻译：功率放大器
公开(公告)号：US20090096525A1
公开(公告)日：2009-04-16
申请号：US12134464
申请日：2008-06-06
申请人： Robert Bogdan Staszewski , See Taur Lee , Dirk Leipold
发明人： Robert Bogdan Staszewski , See Taur Lee , Dirk Leipold
IPC分类号： H03F3/21 , H03F3/68 , H03F1/02
CPC分类号： H03F3/189 , H03F3/211 , H03F3/602 , H03F2200/541
摘要： Methods to implement power control in a digital power amplifier are described.
摘要翻译：描述了在数字功率放大器中实现功率控制的方法。

70. 发明授权

US07440511B2 Transmit filter 有权
标题翻译：发射滤波器
公开(公告)号：US07440511B2
公开(公告)日：2008-10-21
申请号：US10001448
申请日：2001-10-31
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H04L27/00
CPC分类号： H03H17/0283 , H04L7/0029
摘要： A transmit filter (100) receives a stream of data symbols (DT_TX) at a baseband symbol clock rate. An available clock (FREF) is used to generate sample points for producing a generating an oversampled signal. The available clock is independent from the baseband symbol clock, and does not need to be an integer multiple of the clock. Upon identifying a start sequence in the data stream, a phase tracking circuit (106) is used to determine a current position relative to the baseband symbol clock. A state circuit (104) stores the last three, or more, data symbols. Based on the last three data symbols (which determines the shape of the curve for the current data symbol) and the current position (which determines the current position on the curve), a filter circuit (108) generates a sample point.
摘要翻译：发射滤波器（100）以基带符号时钟速率接收数据符号流（DT_TX）。可用时钟（FREF）用于产生用于产生过采样信号的采样点。可用时钟独立于基带符号时钟，不需要是时钟的整数倍。在识别数据流中的起始序列时，使用相位跟踪电路（106）来确定相对于基带符号时钟的当前位置。状态电路（104）存储最后三个或更多数据符号。基于最后三个数据符号（其确定当前数据符号的曲线的形状）和当前位置（其确定曲线上的当前位置），滤波器电路（108）产生采样点。

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