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61. 发明申请

US20140062563A1 CONTROLLING IMPEDANCE OF A SWITCH USING HIGH IMPEDANCE VOLTAGE SOURCES TO PROVIDE MORE EFFICIENT CLOCKING 有权
标题翻译：使用高阻抗电压源开关的控制阻抗提供更有效的时钟
公开(公告)号：US20140062563A1
公开(公告)日：2014-03-06
申请号：US13601155
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger
发明人： Visvesh S. Sathe , Samuel D. Naffziger
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F1/04
摘要： A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.
摘要翻译：集成电路的时钟系统包括形成开关的第一和第二晶体管，该开关用于在谐振工作模式和非谐振工作模式之间切换时钟系统。电感器在谐振模式下形成具有时钟系统的电容的谐振电路。当开关闭合时，开关接收时钟信号并将时钟信号提供给电感器，当开关断开时，断开电感与时钟系统的连接。第一和第二高阻抗电压源向开关提供相应的第一和第二电压，并且第一晶体管的栅极电压以围绕第一电压的时钟信号转变，并且第二晶体管的栅极电压以围绕第二电压的时钟信号转变使得对于第一和第二晶体管保持接近恒定的过驱动电压。

62. 发明授权

US08612781B2 Method and apparatus for application of power density multipliers optimally in a multicore system 有权
标题翻译：在多核系统中最佳应用功率密度乘法器的方法和装置
公开(公告)号：US08612781B2
公开(公告)日：2013-12-17
申请号：US12967535
申请日：2010-12-14
申请人： Samuel D. Naffziger , John P. Petry , Sridhar Sundaram
发明人： Samuel D. Naffziger , John P. Petry , Sridhar Sundaram
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3287 , Y02D10/16 , Y02D10/171
摘要： A method and an apparatus are described that delay application of a higher order Power Density Multiplier (PDM) using a time based moving average of a number of active cores in a multicore system. A PDM is applied to a thermal design power budget of a thermal entity and performance of the thermal entity is increased by transferring available power from a thermal entity not in an active state to a thermal entity in an active state. Sufficient time is allowed for the cooling effect of reduced active cores, to influence the active core that receives the extra power (a higher PDM). Similarly delaying application of a lower PDM with the same moving average, but a different threshold, allows a core to retain a higher power allocation until the more active neighbor core(s) cause it to heat up, thereby boosting core performance.
摘要翻译：描述了使用多核系统中的多个活动核心的基于时间的移动平均来延迟应用较高阶功率密度乘数（PDM）的方法和装置。将PDM应用于热实体的热设计功率预算，并且通过将来自不处于活动状态的热实体的可用功率传递到处于活动状态的热实体的可用功率来增加热实体的性能。允许减少活动核心的冷却效果足够的时间来影响接收额外功率的有源核心（较高的PDM）。类似地延迟具有相同移动平均值但是不同阈值的较低PDM的应用允许核心保持较高的功率分配，直到较活跃的相邻核心使其升温，从而提高核心性能。

63. 发明授权

US08510582B2 Managing current and power in a computing system 有权
标题翻译：管理计算系统中的当前和功率
公开(公告)号：US08510582B2
公开(公告)日：2013-08-13
申请号：US12840813
申请日：2010-07-21
申请人： Samuel D. Naffziger , Sebastien J. Nussbaum
发明人： Samuel D. Naffziger , Sebastien J. Nussbaum
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3243 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A system and method for efficient power transfer on a die. A semiconductor chip comprises on a die two or more computation units (CUs) utilizing at least two different voltage regulators and a power manager. The power manager reallocates power credits across the die when it detects an activity level of a given CU is below a given threshold. In response to receiving a corresponding number of donated power credits, each of the one or more selected CUs maintains a high activity level with a high performance P-state. When a corresponding workload increases, each CU maintains operation and an average power consumption corresponding to the high performance P-state by alternating between at least two different operational voltages. When the operational voltage drops during the alternation, the current drawn by the particular CU may exceed a given current limit. The power manager detects this current limit is exceeded and accordingly reallocates the power credits across the die.
摘要翻译：一种用于模具上有效功率传输的系统和方法。半导体芯片在裸片上包括利用至少两个不同的电压调节器和功率管理器的两个或多个计算单元（CU）。电源管理器在检测到给定CU的活动电平低于给定阈值时，通过芯片重新分配功率信息。响应于接收到相应数量的捐赠功率信用，所述一个或多个所选择的CU中的每一个保持具有高性能P状态的高活动级别。当相应的工作量增加时，每个CU通过在至少两个不同的操作电压之间交替来维持对应于高性能P状态的操作和平均功耗。当交变期间工作电压下降时，由特定CU吸引的电流可能会超过给定的电流限制。电源管理器检测到超出此电流限制，从而重新分配芯片上的功率信息。

64. 发明申请

US20120105129A1 APPARATUS FOR MONOLITHIC POWER GATING ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路上进行单相功率增益的装置
公开(公告)号：US20120105129A1
公开(公告)日：2012-05-03
申请号：US12914110
申请日：2010-10-28
申请人： Samuel D. Naffziger , Bruce Gieseke , Benjamin Beker
发明人： Samuel D. Naffziger , Bruce Gieseke , Benjamin Beker
IPC分类号： H03K17/56
CPC分类号： H01L23/5286 , H01L23/50 , H01L2224/16
摘要： A power gating apparatus includes an integrated circuit package with a first voltage reference plane and a second voltage reference plane, and an integrated circuit that includes a circuit block, and a switch block. The first and second voltage reference planes may be electrically isolated from one another. The switch block may include a plurality of switches arranged in a ring surrounding the circuit block. The first voltage reference plane may be electrically coupled between an external voltage reference and the plurality of switches, and the second voltage reference plane may be electrically coupled between the plurality of switches and the circuit block. The second voltage reference plane may also distribute an electric current throughout the circuit block. In addition, each of the switches is configured to interrupt an electrical path between the first reference voltage plane and the circuit block in response to a control signal.
摘要翻译：电源门控装置包括具有第一电压参考平面和第二电压参考平面的集成电路封装，以及包括电路块的集成电路和开关块。第一和第二电压参考平面可以彼此电隔离。开关块可以包括布置在围绕电路块的环中的多个开关。第一电压参考平面可以电耦合在外部参考电压和多个开关之间，并且第二电压参考平面可以电耦合在多个开关和电路块之间。第二电压参考平面也可以在整个电路块中分布电流。此外，每个开关被配置为响应于控制信号中断第一参考电压平面和电路块之间的电路径。

65. 发明申请

US20120066535A1 MECHANISM FOR CONTROLLING POWER CONSUMPTION IN A PROCESSING NODE 有权
标题翻译：控制加工节能中的功耗的机制
公开(公告)号：US20120066535A1
公开(公告)日：2012-03-15
申请号：US12881307
申请日：2010-09-14
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system includes a plurality of processor cores and a power management unit. The power management unit may be configured to independently control the performance of the processor cores by selecting a respective thermal power limit for each of the plurality of processor cores dependent upon an operating state of each of the processor cores and a relative physical proximity of each processor core to each other processor core. In response to the power management unit detecting that a given processor core is operating above the respective thermal power limit, the power management unit may reduce the performance of the given processor core, and thereby reduce the power consumed by that core.
摘要翻译：系统包括多个处理器核心和电源管理单元。功率管理单元可以被配置为通过根据每个处理器核心的操作状态和每个处理器的相对物理接近度来选择对于多个处理器核心中的每一个的相应的热功率限制来独立地控制处理器核心的性能核心到对方处理器核心。响应于电源管理单元检测到给定的处理器内核正在高于相应的热功率限制，功率管理单元可以降低给定的处理器核心的性能，从而减少该核心的功耗。

66. 发明授权

US08103941B2 Low overhead soft error tolerant flip flop 有权
标题翻译：低开销的软容错触发器
公开(公告)号：US08103941B2
公开(公告)日：2012-01-24
申请号：US12059543
申请日：2008-03-31
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G06F11/00
CPC分类号： H03K19/007 , H03K3/037
摘要： A system and method for soft error recovery (SER) within a flip-flop. A first stage of the flip-flop receives an ungated input clock signal. A second stage of the flip-flop receives a gated input clock signal. The second stage may also store a prebuffered data output and one or more feedback storage values on separate nodes. The flip-flop has SER circuitry used to recover the prebuffered data output and any feedback storage value without requiring a transition of a clock signal.
摘要翻译：触发器内的软错误恢复（SER）的系统和方法。触发器的第一级接收非门控输入时钟信号。触发器的第二级接收门控输入时钟信号。第二阶段还可以在单独的节点上存储预缓冲数据输出和一个或多个反馈存储值。触发器具有用于恢复预缓冲数据输出和任何反馈存储值的SER电路，而不需要时钟信号的转换。

67. 发明申请

US20110314312A1 MANAGING MULTIPLE OPERATING POINTS FOR STABLE VIRTUAL FREQUENCIES 有权
标题翻译：管理稳定的虚拟频率的多个操作要点
公开(公告)号：US20110314312A1
公开(公告)日：2011-12-22
申请号：US12819777
申请日：2010-06-21
申请人： Samuel D. Naffziger , John D. Petry , William A. Hughes
发明人： Samuel D. Naffziger , John D. Petry , William A. Hughes
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points.
摘要翻译：一种用于管理多个离散工作点以创建稳定的虚拟操作点的系统和方法。处理器内的一个或多个功能块产生对应于与相应功能块相关联的活动级别的数据。功率管理器基于每个给定采样间隔一次的数据来确定功耗值。此外，功率管理器确定在热设计功率（TDP）和功耗值之间随时间的经签名的积分差。功率管理器基于签名累积差和给定阈值的比较来选择下一个功率性能状态（P状态）。以这种方式在P状态之间转换，而工作负载不会显着变化，导致处理器在支持的离散工作点之间的虚拟工作点运行。

68. 发明授权

US08010824B2 Sampling chip activity for real time power estimation 有权
标题翻译：用于实时功率估计的采样芯片活动
公开(公告)号：US08010824B2
公开(公告)日：2011-08-30
申请号：US12101598
申请日：2008-04-11
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G06F1/32 , G06F11/30
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system and method for real-time power estimation. A core may be divided into units. Each unit is simulated to achieve a real power consumption characterization. The power consumption is sampled. Statistical analysis is performed that assumes the core has node capacitance switching behavior that is approximated by a stationary random process with a Poisson distribution. The statistical analysis determines the number of samples to take during a sample interval. The operational frequency, sample interval, and number of samples are used to determine the number of signals to sample. Signals are chosen that have a high correlation with the node capacitance switching behavior, such as clock enable signals on the last stage of a clock distribution system. Weights with tuned values are assigned to each sampled signal. Sampling occurs during every predetermined number of clock cycles. The weights of asserted sampled signals are summed in order to determine a repeatable power estimation value.
摘要翻译：一种用于实时功率估计的系统和方法。核心可分为单位。模拟每个单元以实现真正的功耗表征。对功耗进行采样。执行统计分析，假定核心具有由具有泊松分布的静态随机过程近似的节点电容切换行为。统计分析确定在采样间隔期间采样的数量。使用操作频率，采样间隔和采样数量来确定采样信号的数量。选择与节点电容切换行为高度相关的信号，例如时钟分配系统的最后阶段的时钟使能信号。具有调谐值的重量被分配给每个采样信号。在每个预定数量的时钟周期内进行采样。所确定的采样信号的权重被相加以便确定可重复的功率估计值。

69. 发明申请

US20100122101A1 METHOD AND APPARATUS FOR REGULATING POWER CONSUMPTION 有权
标题翻译：调节功耗的方法和装置
公开(公告)号：US20100122101A1
公开(公告)日：2010-05-13
申请号：US12268531
申请日：2008-11-11
申请人： Samuel D. Naffziger , Sebastien J. Nussbaum
发明人： Samuel D. Naffziger , Sebastien J. Nussbaum
IPC分类号： G06F1/30
CPC分类号： G06F1/206 , G06F1/3203 , G06F9/50 , Y02D10/16 , Y02D10/22
摘要： A method for controlling power consumption while maximizing processor performance. The method includes, for a time interval of operation in a first operational state, determining an amount of power consumed during by one or more cores of a processor, calculating, a power error based on the amount of power consumed in the time interval, obtaining a power error term for the interval by adding the power error to a power error term from a previous time interval, and comparing the power error term to at least a first error threshold. If the power error term is outside a range defined at least in part by the first error threshold, the method exits the first operational state and enters a second operational state. If the power error term is within the range defined at least in part by the first error threshold, operation continues in the first operational state.
摘要翻译：一种在最大化处理器性能的同时控制功耗的方法。该方法包括：在第一操作状态下的操作的时间间隔中，确定处理器的一个或多个核心期间消耗的功率量，基于在该时间间隔中消耗的功率量来计算功率误差，获得通过将功率误差添加到来自前一时间间隔的功率误差项，以及将功率误差项与至少第一误差阈值进行比较来计算间隔的功率误差项。如果功率误差项在至少部分由第一误差阈值限定的范围之外，则该方法退出第一操作状态并进入第二操作状态。如果功率误差项在至少部分地由第一误差阈值限定的范围内，则操作在第一操作状态下继续。

70. 发明申请

US20090300329A1 VOLTAGE DROOP MITIGATION THROUGH INSTRUCTION ISSUE THROTTLING 有权
标题翻译：通过指导发生电压的电压减速
公开(公告)号：US20090300329A1
公开(公告)日：2009-12-03
申请号：US12127514
申请日：2008-05-27
申请人： Samuel D. Naffziger , Michael Gerard Butler
发明人： Samuel D. Naffziger , Michael Gerard Butler
IPC分类号： G06F9/312
CPC分类号： G06F1/3203 , G06F9/3836 , G06F9/3869
摘要： A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with available source data, the corresponding weight values are summed together to produce a local current consumption value and this value is summed with any existing global current consumption values from corresponding schedulers of other processor cores yielding an activity event. The activity event is stored. Hashing functions within the scheduler are used to determine both a recent and an old activity average using the calculated activity event and stored older activity events. Instruction issue throttling occurs if either a difference between the old activity average and the recent activity average exceed a first threshold or the recent activity average exceeds a second threshold.
摘要翻译：一种用于提供数字实时电压下降检测和随后的电压下降降低的系统和方法。保留站内的调度器可以存储对应于从硅硅功率建模分析得到的指令的节点电容切换活动的每个指令的权重值。对于使用可用源数据选择的指令，将相应的权重值相加在一起以产生局部电流消耗值，并将该值与来自产生活动事件的其他处理器核心的相应调度器的任何现有全局电流消耗值相加。活动事件被存储。调度程序中的散列函数用于使用计算的活动事件和存储的较旧活动事件来确定最近和旧活动平均值。如果旧活动平均值与近期活动平均值之间的差异超过第一阈值或近期活动平均值超过第二阈值，就会发生指令问题调节。

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