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61. 发明申请

US20120075947A1 Semiconductor Memory Devices Having Self-Refresh Capability 有权
标题翻译：具有自刷新能力的半导体存储器件
公开(公告)号：US20120075947A1
公开(公告)日：2012-03-29
申请号：US13241977
申请日：2011-09-23
申请人： Yong Hoon Kang , Joo Young Hwang , Jae Young Choi , Young Joon Choi
发明人： Yong Hoon Kang , Joo Young Hwang , Jae Young Choi , Young Joon Choi
IPC分类号： G11C11/402
CPC分类号： G11C11/40615 , G11C11/40618
摘要： A semiconductor memory device is provided. The semiconductor memory device includes at least one memory bank including a plurality of memory cells and a self-refresh controller configured to generate a refresh address and to output a row address for a page to be refreshed based on the refresh address. The semiconductor memory device drives the at least one memory bank based on the row address and selectively refreshes pages in the at least one memory bank in response to the row address.
摘要翻译：提供半导体存储器件。半导体存储器件包括至少一个包括多个存储器单元的存储器组和一个自刷新控制器，该自刷新控制器被配置为产生刷新地址，并且基于刷新地址输出要刷新的页面的行地址。半导体存储器设备基于行地址驱动至少一个存储体，并响应于行地址选择性地刷新至少一个存储体中的页面。

62. 发明申请

US20120033519A1 TEMPERATURE ALERT AND LOW RATE REFRESH FOR A NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的温度警报和低速刷新
公开(公告)号：US20120033519A1
公开(公告)日：2012-02-09
申请号：US13142418
申请日：2008-12-30
申请人： Emanuele Confalonieri , Daniele Balluchi
发明人： Emanuele Confalonieri , Daniele Balluchi
IPC分类号： G11C11/402
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0033 , G11C16/3431
摘要： A method and apparatus are described for measuring a temperature within a non-volatile memory, storing, in a register within the non-volatile memory, a temperature alert comprising one or more bits indicating the non-volatile memory has exceeded a threshold temperature for a period of time, determining, by a host, that the temperature alert is active, and in response to the determination that the temperature alert is active, refreshing at least a portion of the non-volatile memory.
摘要翻译：描述了一种用于测量非易失性存储器内的温度的方法和装置，其在非易失性存储器内的寄存器中存储包括指示非易失性存储器的一个或多个位的温度警报已超过阈值温度时间段，由主机确定温度警报是活动的，并且响应于温度警报激活的确定，刷新至少一部分非易失性存储器。

63. 发明申请

US20110286287A1 SEMICONDUCTOR MEMORY DEVICE WITH OPTIMUM REFRESH CYCLE ACCORDING TO TEMPERATURE VARIATION 失效
标题翻译：具有根据温度变化的最佳刷新周期的半导体存储器件
公开(公告)号：US20110286287A1
公开(公告)日：2011-11-24
申请号：US13196779
申请日：2011-08-02
申请人： Se-Jun KIM , Sang-Hoon Hong , Jae-Bum Ko
发明人： Se-Jun KIM , Sang-Hoon Hong , Jae-Bum Ko
IPC分类号： G11C11/402 , G11C7/00
CPC分类号： G11C11/40626 , G11C11/406 , G11C2211/4061
摘要： Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage.
摘要翻译：公开了一种用于在半导体器件中产生刷新信号的方法和用于在半导体存储器件中执行刷新操作的方法。一种产生刷新信号的方法包括测量半导体存储器件的温度，基于测量的温度产生温度控制电压，基于温度控制电压产生N位数字信号，并产生频率为由N位数字信号决定。产生温度控制电压包括产生在测量温度降低时增加的第一电流，并且随着测量温度的升高而降低，并产生温度控制电压。

64. 发明申请

US20110242913A1 SELF REFRESH CIRCUIT 有权
标题翻译：自我修复电路
公开(公告)号：US20110242913A1
公开(公告)日：2011-10-06
申请号：US13035230
申请日：2011-02-25
申请人： Yun Seok HONG
发明人： Yun Seok HONG
IPC分类号： G11C11/402
CPC分类号： G11C11/406 , G11C11/40615 , G11C2211/4067
摘要： A self refresh circuit includes a continuous output interrupting unit and a glitch removing unit. The continuous output interrupting unit is configured to receive a delay self refresh signal, transmit a pulse of an internal active signal as a first output active signal and interrupt the transmission of the pulse of the internal active signal during a first time period. The glitch removing unit is configured to generate and output a second output active signal when the first output active signal has a predetermined pulse width.
摘要翻译：自刷新电路包括连续输出中断单元和毛刺去除单元。连续输出中断单元被配置为接收延迟自刷新信号，将内部有效信号的脉冲作为第一输出有效信号发送，并且在第一时间段期间中断内部有效信号的脉冲的传输。毛刺去除单元被配置为当第一输出有效信号具有预定的脉冲宽度时产生并输出第二输出有效信号。

65. 发明申请

US20110235409A1 SEMICONDUCTOR MEMORY DEVICE FOR WRITING DATA TO MULTIPLE CELLS SIMULTANEOUSLY AND REFRESH METHOD THEREOF 有权
标题翻译：用于将数据写入多个单元的半导体存储器件及其更新方法
公开(公告)号：US20110235409A1
公开(公告)日：2011-09-29
申请号：US13152692
申请日：2011-06-03
申请人： HEE BOK KANG , SUK KYOUNG HONG
发明人： HEE BOK KANG , SUK KYOUNG HONG
IPC分类号： G11C11/402
CPC分类号： G11C13/003 , G11C8/06 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C16/3431 , G11C2013/0052 , G11C2013/0078 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/72 , G11C2213/75 , G11C2213/76
摘要： A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.
摘要翻译：半导体存储器件包括被配置为提供单元驱动电压的读/写位线。选择单元连接到读/写位线并由字线控制。多个单元连接在选择单元和源极线之间，并且单元被配置为根据单元驱动电压来读取和写入数据。多个开关元件的每个开关元件与多个单元的单个单元并联连接，并且多个开关元件由多个位线选择性地控制。

66. 发明申请

US20110116333A1 MEMORY TEST APPARATUS AND TESTING METHOD 有权
标题翻译：记忆测试装置和测试方法
公开(公告)号：US20110116333A1
公开(公告)日：2011-05-19
申请号：US12990983
申请日：2009-05-07
申请人： Takashi Nakamura
发明人： Takashi Nakamura
IPC分类号： G11C29/08 , G11C11/402
CPC分类号： G11C29/56 , G11C11/401 , G11C29/50016 , G11C29/56012
摘要： A refresh control circuit receives an interrupt signal, which is a request to refresh DRAM (Dynamic Random Access Memory) and which is asserted at predetermined timings. The refresh control circuit counts the number of times the interrupt signal is asserted, and asserts an interrupt subroutine start signal, which is an instruction to refresh the DRAM, in an idle state in which the DRAM is accessible from an external circuit, for a number of times that is equal to the number of times thus counted. When the interrupt subroutine start signal is asserted, a refresh circuit executes a predetermined interrupt subroutine, and supplies a refresh pattern to the DRAM.
摘要翻译：刷新控制电路接收中断信号，该中断信号是刷新DRAM（动态随机存取存储器）的请求，并且以预定的定时被断言。刷新控制电路对中断信号被断言的次数进行计数，并且在可从外部电路访问DRAM的空闲状态下断言作为刷新DRAM的指令的中断子程序开始信号，数量的次数等于这样计算的次数。当中断子程序启动信号有效时，刷新电路执行预定的中断子程序，并向DRAM提供刷新模式。

67. 发明申请

US20110116326A1 Refresh Signal Generating Circuit 有权
标题翻译：刷新信号发生电路
公开(公告)号：US20110116326A1
公开(公告)日：2011-05-19
申请号：US13015344
申请日：2011-01-27
申请人： Sang Kwon Lee
发明人： Sang Kwon Lee
IPC分类号： G11C7/10 , G11C11/402
CPC分类号： G11C11/406 , G11C7/222 , G11C7/225 , G11C11/40615 , G11C11/4076 , G11C2211/4065
摘要： A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.
摘要翻译：半导体存储器件的刷新信号产生电路包括一个标志信号发生器，该标志信号发生器响应于刷新信号和一个预充电信号产生一个标志信号;一个时钟使能信号缓冲器，其基于外部时钟使能产生第一和第二缓冲器使能信号响应于标志信号的信号，以及片选信号缓冲器，其响应于标志信号，基于外部片选信号产生内部片选信号。

68. 发明申请

US20110116309A1 Refresh Circuitry for Phase Change Memory 有权
标题翻译：相变存储器的刷新电路
公开(公告)号：US20110116309A1
公开(公告)日：2011-05-19
申请号：US13011691
申请日：2011-01-21
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： G11C11/402 , G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0033 , G11C13/004 , G11C16/3431
摘要： A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.
摘要翻译：如本文所述的存储器件包括相变存储器单元的参考阵列和相变存储器单元的存储器阵列，其中存储在参考阵列中的当前数据集与预期数据集之间的差用于确定何时刷新内存阵列。用于参考阵列的高电阻状态是具有比用于存储器阵列的高电阻状态的最小电阻的最小电阻的“部分复位”状态。感测电路适于读取参考阵列的存储器单元，并且如果存储在参考阵列中的当前数据集与预期数据组之间存在差异，则产生刷新命令信号，以及响应于刷新命令信号的控制电路对存储器阵列的存储单元执行刷新操作。

69. 发明申请

US20110103169A1 DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS 有权
标题翻译：动态随机访问存储器件和自我修复存储器单元的方法
公开(公告)号：US20110103169A1
公开(公告)日：2011-05-05
申请号：US13004461
申请日：2011-01-11
申请人： HakJune OH
发明人： HakJune OH
IPC分类号： G11C11/402
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40615 , G11C11/40626
摘要： A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal. In response to the oscillation signal, a self-request controller provides a self-refresh request signal in the self-refresh mode. The self-refresh signal is asynchoronized with the self-fresh mode signal and is provided to an address circuit to select a wordline for refreshing the memory cells thereof. The self-refresh request controller includes logic circuitry for arbitrating timing between initial active edges of the oscillation signal and the self-refresh mode signal and providing the self-refresh request and ceasing it, regardless of conflict between the self-refresh mode signal and the oscillation signal upon self-refresh mode entry and exit. The DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.
摘要翻译：具有存储单元的动态随机存取存储器（DRAM）装置在自刷新模式和正常模式下操作。模式检测器在自刷新操作模式下提供自刷新模式信号。它包括一个自由运行的振荡器，用于产生独立于自刷新模式信号的振荡信号。响应于振荡信号，自请求控制器在自刷新模式下提供自刷新请求信号。自刷新信号与自清晰模式信号异步化，并被提供给地址电路以选择用于刷新其存储单元的字线。自刷新请求控制器包括逻辑电路，用于仲裁振荡信号的初始有效边沿与自刷新模式信号之间的定时，并提供自刷新请求并停止它，而不管自刷新模式信号和自刷新模式进入和退出时的振荡信号。 DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。

70. 发明授权

US06853022B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06853022B2
公开(公告)日：2005-02-08
申请号：US10352987
申请日：2003-01-29
申请人： Tsuyoshi Koga , Yoshiyuki Ishigaki , Motoi Ashida , Yukio Maki , Yasuhiro Fujii , Tomohiro Hosokawa , Takashi Terada , Makoto Dei , Yasuichi Masuda
发明人： Tsuyoshi Koga , Yoshiyuki Ishigaki , Motoi Ashida , Yukio Maki , Yasuhiro Fujii , Tomohiro Hosokawa , Takashi Terada , Makoto Dei , Yasuichi Masuda
IPC分类号： H01L27/108 , G11C11/402 , G11C11/412 , H01L21/8242 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/4023 , G11C11/412 , H01L27/108 , H01L27/10844 , H01L27/11 , H01L27/1108
摘要： A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.
摘要翻译：一种半导体存储器件，其主要存储部分是存储电荷作为二进制信息的电容器，以及控制向电容器的电荷输入/输出的存取晶体管，并且不需要刷新。半导体存储器件包括具有存储节点的电容器，该存储节点位于半导体衬底之上，并且保持对应于存储的二进制信息的逻辑电平的电荷，位于半导体衬底表面上的存取晶体管，并控制累积在该半导体衬底表面上的电荷的输入/输出电容器和位于半导体衬底上的锁存电路，并保持电容器存储节点的电位。构成锁存电路的电路元件中的至少一个位于存取晶体管的上方。

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