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71. 发明授权

US07787279B2 Integrated circuit having a resistive memory 有权
标题翻译：具有电阻存储器的集成电路
公开(公告)号：US07787279B2
公开(公告)日：2010-08-31
申请号：US11441805
申请日：2006-05-26
申请人： Thomas D. Happ , Cay-Uwe Pinnow , Ralf Symanczyk , Klaus-Dieter Ufert
发明人： Thomas D. Happ , Cay-Uwe Pinnow , Ralf Symanczyk , Klaus-Dieter Ufert
IPC分类号： G11C11/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1666
摘要： An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.
摘要翻译：集成半导体存储器包括布置在两个电极（10,20）之间的存储介质（6），该存储介质可以是例如相变介质。存储介质（6）可以通过电流进入第一状态或第二状态，结果可以存储信息项。根据本发明的实施例，提供了一种层状平面（L），其中嵌入由材料（4）制成的杂质颗粒，结果存储介质中的电流密度局部增加，并且需要编程电流重编程减少。结果，包含相变介质的存储元件的电流消耗减少，使得它们可以首次以最小的特征尺寸与其他元件（例如晶体管）一体化，并且集成到单个半导体电路中，并且不存在更长的时间必须在单独的子电路中排列。

72. 发明授权

US07786621B2 Circuit arrangement and method for reducing electromagnetic interference 有权
标题翻译：降低电磁干扰的电路布置及方法
公开(公告)号：US07786621B2
公开(公告)日：2010-08-31
申请号：US11550933
申请日：2006-10-19
申请人： Mojtaba Joodaki
发明人： Mojtaba Joodaki
IPC分类号： H04B3/30
CPC分类号： H04B15/04
摘要： Circuit arrangement and method for reducing electromagnetic interference. The circuit arrangement includes a supply potential connection, a reference-ground potential connection, a controllable impedance element, a signal generator, and a circuit unit. The controllable impedance element is connected between the supply potential connection and the reference-ground potential connection, and has a control connection for receiving a control signal for controlling the impedance of the impedance element. The signal generator is coupled to the control connection of the impedance element. The circuit unit is connected between the supply potential connection and the reference-ground potential connection, and originates the electromagnetic interference during operation. The signal generator is designed to produce the control signal, which varies over time, in such a manner that the electromagnetic interference which originates from the circuit unit during operation is changed.
摘要翻译：降低电磁干扰的电路布置及方法。电路装置包括电源电位连接，参考地电位连接，可控阻抗元件，信号发生器和电路单元。可控阻抗元件连接在电源电位连接和基准 - 接地电位连接之间，并且具有用于接收用于控制阻抗元件的阻抗的控制信号的控制连接。信号发生器耦合到阻抗元件的控制连接。电路单元连接在电源电位连接和基准 - 接地电位连接之间，并在操作过程中产生电磁干扰。信号发生器被设计成产生随时间变化的控制信号，使得在操作期间源自电路单元的电磁干扰改变。

73. 发明授权

US07785953B2 Method for forming trenches on a surface of a semiconductor substrate 有权
标题翻译：在半导体衬底的表面上形成沟槽的方法
公开(公告)号：US07785953B2
公开(公告)日：2010-08-31
申请号：US12112379
申请日：2008-04-30
申请人： Josef Willer , Michael Specht , Christoph Friederich , Doris Keitel-Schulz
发明人： Josef Willer , Michael Specht , Christoph Friederich , Doris Keitel-Schulz
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/31053 , H01L21/3212 , H01L29/66825 , H01L29/7881
摘要： A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.
摘要翻译：描述了在半导体衬底的表面上形成沟槽的方法。该方法可以包括：将第一多个沟槽蚀刻到半导体衬底的表面中; 用至少一种材料填充所述第一多个沟槽; 以及将第二多个沟槽蚀刻到所述第一多个沟槽的每个第二沟槽中。此外，描述了在半导体衬底和集成电路上形成浮置栅电极的方法。

74. 发明授权

US07781773B2 Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array 有权
标题翻译：用于半导体存储器件的晶体管阵列和用于制造垂直沟道晶体管阵列的方法
公开(公告)号：US07781773B2
公开(公告)日：2010-08-24
申请号：US12042822
申请日：2008-03-05
申请人： Andreas Thies , Klaus Muemmler
发明人： Andreas Thies , Klaus Muemmler
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , G11C7/02 , G11C7/18 , H01L27/10852 , H01L27/10876 , H01L27/10891 , Y10S257/905
摘要： A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.
摘要翻译：提供了一种用于半导体存储器件的晶体管阵列。从半导体衬底的本体部分向外延伸的多个半导体柱以行和列布置。每个柱形成垂直通道存取晶体管的有源区。绝缘沟槽形成在支柱之间。掩埋字线沿绝缘沟槽沿支柱排延伸。位线槽形成在柱柱之间。位线在位线沟槽的下部垂直于字线延伸。柱子的第一列和第二列面对每个位线。每个位线经由由多晶硅形成的单面位线接触件耦合到第一柱柱的支柱中的有源区域，并且与第二柱柱的柱的有源区域绝缘。

75. 发明授权

US07772580B2 Integrated circuit having a cell with a resistivity changing layer 有权
标题翻译：具有具有电阻率变化层的单元的集成电路
公开(公告)号：US07772580B2
公开(公告)日：2010-08-10
申请号：US11837380
申请日：2007-08-10
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L29/02
CPC分类号： H01L45/149 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/065 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/1683
摘要： In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.
摘要翻译：在本发明的实施例中，提供了具有单元的集成电路。电池可以包括场效应晶体管结构，其包括设置在栅极堆叠上方的栅极堆叠和电阻率变化材料结构，其中电阻率变化材料结构包括电阻率变化材料，其被配置为响应于应用对电阻率变化材料结构的电压。

76. 发明授权

US07771206B2 Horizontal dual in-line memory modules 有权
标题翻译：水平双列直插式内存模块
公开(公告)号：US07771206B2
公开(公告)日：2010-08-10
申请号：US12209019
申请日：2008-09-11
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： H01R12/00
CPC分类号： H05K1/141 , H05K1/144 , H05K3/326 , H05K3/328 , H05K3/366 , H05K3/4092 , H05K2201/0397 , H05K2201/042 , H05K2201/045 , H05K2201/10159 , H05K2203/049
摘要： Horizontal dual in-line memory modules are disclosed. In one embodiment, the memory module includes a circuit board, a plurality of memory chips attached to a top surface of the circuit board, and a plurality of connector contacts disposed under a back surface of the circuit board and extending away from the memory chips, the connector contacts being electrically coupled to the memory chips, the back surface opposite the top surface of the circuit board.
摘要翻译：公开了水平双列直插式存储器模块。在一个实施例中，存储器模块包括电路板，附接到电路板的顶表面的多个存储器芯片以及设置在电路板的背面下方并远离存储器芯片延伸的多个连接器触点，连接器触点电耦合到存储器芯片，背面与电路板的顶表面相对。

77. 发明授权

US07763987B2 Integrated circuit and methods of manufacturing a contact arrangement and an interconnection arrangement 失效
标题翻译：集成电路和制造接触装置和互连装置的方法
公开(公告)号：US07763987B2
公开(公告)日：2010-07-27
申请号：US11679295
申请日：2007-02-27
申请人： Lars Bach
发明人： Lars Bach
IPC分类号： H01L21/4763
CPC分类号： H01L27/0207 , H01L21/7681 , H01L21/76816 , H01L21/76897 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A contact arrangement is manufactured by providing a substrate that includes first regions that are arranged along a row direction and a second region. An interlayer is provided that covers the first regions and the second region. A buried mask including a first trim opening above the first regions is provided. A top mask including first template openings is provided, where each first template opening is arranged above one of the first regions. A second template opening is provided above the second region. The fill material and the interlayer are etched to form contact trenches above the first regions and the second region. Substrate area efficient chains of evenly spaced contacts are provided.
摘要翻译：通过提供包括沿着行方向布置的第一区域和第二区域的基板来制造接触装置。提供覆盖第一区域和第二区域的中间层。提供了包括在第一区域上方的第一修剪开口的掩埋掩模。提供包括第一模板开口的顶部掩模，其中每个第一模板开口布置在第一区域之上。第二模板开口设置在第二区域的上方。蚀刻填充材料和中间层以在第一区域和第二区域之上形成接触沟槽。提供均匀间隔触点的基板区域有效链。

78. 发明授权

US07759704B2 Memory cell array comprising wiggled bit lines 失效
标题翻译：包含摆动位线的存储单元阵列
公开(公告)号：US07759704B2
公开(公告)日：2010-07-20
申请号：US12252853
申请日：2008-10-16
申请人： Martin Popp , Till Schloesser
发明人： Martin Popp , Till Schloesser
IPC分类号： H01L27/10
CPC分类号： H01L27/10885 , H01L27/10882 , H01L27/10888 , H01L27/10891
摘要： An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.
摘要翻译：包括存储单元阵列的集成电路包括沿着并行有源区域线，位线布置的晶体管，位线被布置成使得各个相互交叉的多个有源区域线分别形成位线接触，位线形成为摆动的线条，字线被布置成使得字线中的单个字符与多个有效区域线相交，并且字线中的单个字符与多个位线相交，其中相邻的位线接触，其中每一个连接到一个的有源面积线与不同的位线连接。

79. 发明授权

US07755936B2 Integrated circuits, cell, cell arrangement, method of reading a cell, memory module 失效
标题翻译：集成电路，单元，单元布置，读取单元的方法，存储器模块
公开(公告)号：US07755936B2
公开(公告)日：2010-07-13
申请号：US12020902
申请日：2008-01-28
申请人： Joachim Wecker , Manfred Ruehrig
发明人： Joachim Wecker , Manfred Ruehrig
IPC分类号： G11C7/00
CPC分类号： G11C11/16 , G11C5/02 , G11C11/1675
摘要： An embodiment of the invention provides an integrated circuit having a cell. The cell includes a first magnetic layer structure having a first magnetization along a first axis, a non-magnetic spacer layer structure disposed above the first magnetic layer structure, and a second magnetic layer structure disposed above the non-magnetic spacer layer structure. The second magnetic layer structure has a second magnetization along a second axis that is arranged in an angle with regard to the first axis such that by changing the direction of the second magnetization, the direction of the first magnetization along the first axis can be determined.
摘要翻译：本发明的实施例提供了一种具有单元的集成电路。电池包括具有沿着第一轴的第一磁化的第一磁性层结构，以及设置在第一磁性层结构之上的非磁性间隔层结构，以及设置在非磁性间隔层结构之上的第二磁性层结构。第二磁性层结构沿着第二轴线具有相对于第一轴线成一定角度的第二磁化，使得通过改变第二磁化的方向，可以确定沿第一轴线的第一磁化方向。

80. 发明授权

US07731928B2 Silanized carbon nanotubes and method for the production thereof 失效
标题翻译：硅烷化碳纳米管及其制备方法
公开(公告)号：US07731928B2
公开(公告)日：2010-06-08
申请号：US11569900
申请日：2005-04-21
申请人： Georg Duesberg , Maik Liebau , Eugen Unger
发明人： Georg Duesberg , Maik Liebau , Eugen Unger
IPC分类号： D01F9/12
CPC分类号： C09C1/44 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B32/168 , C01B2202/06 , C01P2004/13
摘要： A process for silanizing carbon nanotubes, wherein the carbon nanotubes are oxidized and subsequently exposed to a saturated gas phase including one or more organosilane derivatives which form covalent bonds to the carbon nanotubes with siloxane formation.
摘要翻译：一种使碳纳米管硅烷化的方法，其中碳纳米管被氧化并随后暴露于包含一个或多个有机硅烷衍生物的饱和气相，该有机硅烷衍生物与形成硅氧烷的碳纳米管共价键。

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