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1. 发明授权

US08125006B2 Array of low resistive vertical diodes and method of production 失效
标题翻译：低电阻垂直二极管阵列及其制作方法
公开(公告)号：US08125006B2
公开(公告)日：2012-02-28
申请号：US12188401
申请日：2008-08-08
申请人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： H01L29/768
CPC分类号： H01L27/24 , Y10S257/91
摘要： An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.
摘要翻译：描述了包括存储器单元阵列和相应的制造方法的集成电路。每个存储单元包括电阻切换存储器元件和耦合到选择线沟槽中的选择线的垂直选择二极管，用于从多个存储器单元中选择一个单元。选择线在选择线沟槽的一个垂直侧壁处耦合到垂直选择二极管。

2. 发明授权

US07952138B2 Memory circuit with field effect transistor and method for manufacturing a memory circuit with field effect transistor 有权
标题翻译：具有场效应晶体管的存储电路和用场效应晶体管制造存储电路的方法
公开(公告)号：US07952138B2
公开(公告)日：2011-05-31
申请号：US11825228
申请日：2007-07-05
申请人： Klaus Muemmler , Peter Baars , Stefan Tegen
发明人： Klaus Muemmler , Peter Baars , Stefan Tegen
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/66666 , H01L27/10876 , H01L27/10894 , H01L29/7827
摘要： An integrated circuit includes a field effect transistor formed in an active area segment of a semiconductor substrate. The transistor comprises: a first source/drain contact region including a first vertical extension and a second source/drain contact region including a second vertical extension and a channel region formed around a recessed channel transistor groove, the groove being formed in the active area segment and extending to a groove depth larger than a lower first contact region depth, wherein the second vertical extension of the second source/drain contact region is arranged above the first extension of the first source/drain contact region, and wherein the recessed channel transistor groove is filled with a conductive gate material at a groove depth lower than the first contact region depth.
摘要翻译：集成电路包括形成在半导体衬底的有源区段中的场效应晶体管。晶体管包括：包括第一垂直延伸的第一源极/漏极接触区域和包括第二垂直延伸部的第二源极/漏极接触区域和形成在凹陷沟道晶体管沟槽周围的沟道区域，所述沟槽形成在有源区域段中并且延伸到大于下部第一接触区域深度的凹槽深度，其中所述第二源极/漏极接触区域的所述第二垂直延伸部布置在所述第一源极/漏极接触区域的所述第一延伸部之上，并且其中所述凹入沟道晶体管沟槽在低于第一接触区域深度的槽深处填充有导电栅极材料。

3. 发明授权

US07851356B2 Integrated circuit and methods of manufacturing the same 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US07851356B2
公开(公告)日：2010-12-14
申请号：US11863528
申请日：2007-09-28
申请人： Stefan Tegen , Klaus Muemmler , Peter Baars , Uta Mierau
发明人： Stefan Tegen , Klaus Muemmler , Peter Baars , Uta Mierau
IPC分类号： H01L21/4763
CPC分类号： H01L21/0274 , H01L21/31144 , H01L21/32139 , H01L21/76808 , H01L21/76816 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within a peripheral region of the substrate. Forming the landing pads and forming the wiring lines includes a common lithographic process being effective in both the array and peripheral regions. The wiring lines and the landing pads of the integrated circuit are self-aligned.
摘要翻译：一种制造集成电路的方法包括在衬底的阵列区域中形成着色焊盘，各个着陆焊盘电耦合到形成在阵列区域中的衬底中的各个器件的部分。该方法还包括在衬底的周边区域内形成布线。形成着陆焊盘并形成布线包括在阵列和周边区域均有效的共同光刻工艺。集成电路的布线和着陆焊盘是自对准的。

4. 发明授权

US07777266B2 Conductive line comprising a capping layer 有权
标题翻译：导电线包括封盖层
公开(公告)号：US07777266B2
公开(公告)日：2010-08-17
申请号：US11947510
申请日：2007-11-29
申请人： Peter Baars , Andreas Eifler , Klaus Muemmler , Stefan Tegen
发明人： Peter Baars , Andreas Eifler , Klaus Muemmler , Stefan Tegen
IPC分类号： H01L29/108
CPC分类号： H01L29/66621 , H01L21/76877 , H01L27/10876 , H01L27/10891 , H01L29/4236
摘要： An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound.
摘要翻译：一种集成电路包括导线，该导线具有由金属构成的导电层或包含金属的第一化合物和由包含金属的第二化合物制成的覆盖层，所述覆盖层与导电层接触，第一化合物与第二化合物不同。

5. 发明授权

US07566611B2 Manufacturing method for an integrated semiconductor structure 失效
标题翻译：集成半导体结构的制造方法
公开(公告)号：US07566611B2
公开(公告)日：2009-07-28
申请号：US11443652
申请日：2006-05-31
申请人： Peter Baars , Klaus Muemmler , Stefan Tegen , Daniel Koehler , Joern Regul
发明人： Peter Baars , Klaus Muemmler , Stefan Tegen , Daniel Koehler , Joern Regul
IPC分类号： H01L21/8234
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10861 , H01L27/10876 , H01L27/10894 , H01L27/10897
摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said memory cell region; removing said mask layer and said first protective layer from said memory cell region; forming a first contact hole between two neighboring gate stacks in said memory cell region, said first contact hole exposing a contact area; forming at least one other contact hole in said peripheral device region, said at least one other contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one other contact hole with a respective contact plug.
摘要翻译：本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：在存储单元区域中提供具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域和外围设备区域上沉积由碳制成的或由含碳材料制成的第一保护层; 在所述存储单元区域中的所述第一保护层上形成掩模层; 通过在蚀刻步骤中去除所述外围设备区域中的所述第一保护层，在所述外围设备区域中暴露所述至少一个栅极堆叠的所述盖，其中所述掩模层用作所述存储单元区域中的掩模; 从所述存储单元区域去除所述掩模层和所述第一保护层; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔，所述第一接触孔暴露接触区域; 在所述外围设备区域中形成至少另一个接触孔，所述至少一个其它接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或位于所述栅极堆叠中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少一个其它接触孔。

6. 发明申请

US20090121315A1 METHOD FOR PRODUCING AN INTEGRATED CIRCUIT AND ARRANGEMENT COMPRISING A SUBSTRATE 有权
标题翻译：用于生产集成电路的方法和包括基板的布置
公开(公告)号：US20090121315A1
公开(公告)日：2009-05-14
申请号：US12269612
申请日：2008-11-12
申请人： Peter Baars , Stefan Tegen , Klaus Muemmler
发明人： Peter Baars , Stefan Tegen , Klaus Muemmler
IPC分类号： H01L29/92 , H01L21/44 , H01L21/20
CPC分类号： H01L28/90 , H01L27/10852
摘要： Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided.
摘要翻译：本发明的实施例涉及一种包括载体的集成电路，其具有具有第一电极和第二电极的电容器。第一电极具有电介质层A层序列布置在载体上，电容器以所述层序列引入，其中层序列具有布置在第一支撑层上方一段距离处的第一支撑层和第二支撑层，其中第一和第二支撑层邻接电容器的第一电极。还提供了制造集成电路的方法。

7. 发明申请

US20070190773A1 Method of fabricating a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070190773A1
公开(公告)日：2007-08-16
申请号：US11352446
申请日：2006-02-10
申请人： Peter Baars , Klaus Muemmler , Stefan Tegen
发明人： Peter Baars , Klaus Muemmler , Stefan Tegen
IPC分类号： H01L21/4763
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10882 , H01L27/10891 , H01L27/10894
摘要： According to the invention, the method comprises the steps of: fabricating a first conductive layer including a first contact pad and covering the first conductive layer with a first protection layer at least on top of the first contact pad such that a first protective cap is formed thereon; fabricating a second conductive layer including a second contact pad, wherein the second conductive layer and the first conductive layer are electrically insulated from one another, and covering the second conductive layer with a second protection layer at least on top of the second contact pad such that a second protective cap is formed thereon; depositing at least one intermediate layer on top of the structure; forming a mask on top of the intermediate layer and etching the intermediate layer thereby exposing the first protective cap and the second protective cap, wherein an etchant is applied that provides a larger etch rate with regard to the intermediate layer than with regard to the protective layer; and after exposing the first and second protective caps, etching them and exposing the first and second contact pad during the same etch step.
摘要翻译：根据本发明，该方法包括以下步骤：制造包括第一接触焊盘并且至少在第一接触焊盘的顶部上的第一保护层覆盖第一导电层的第一导电层，使得形成第一保护盖上; 制造包括第二接触焊盘的第二导电层，其中所述第二导电层和所述第一导电层彼此电绝缘，并且至少在所述第二接触焊盘的顶部上用第二保护层覆盖所述第二导电层，使得在其上形成第二保护盖; 在结构的顶部上沉积至少一个中间层; 在中间层的顶部形成掩模并蚀刻中间层，从而暴露第一保护帽和第二保护帽，其中施加蚀刻剂，相对于保护层而言，相对于中间层提供较大的蚀刻速率 ; 并且在暴露第一和第二保护盖之后，在相同的蚀刻步骤期间蚀刻它们并暴露第一和第二接触焊盘。

8. 发明申请

US20060255384A1 Memory device and method of manufacturing the same 审中-公开
标题翻译：存储器件及其制造方法
公开(公告)号：US20060255384A1
公开(公告)日：2006-11-16
申请号：US11128423
申请日：2005-05-13
申请人： Peter Baars , Klaus Muemmler , Daniel Koehler
发明人： Peter Baars , Klaus Muemmler , Daniel Koehler
IPC分类号： H01L21/8244 , H01L29/94
CPC分类号： H01L28/91 , H01L21/76816 , H01L27/10817 , H01L27/10894
摘要： A memory device includes an array of memory cells and a storage capacitor for storing information. Each memory cell includes an access transistor. The access transistor includes first and second source/drain regions, a channel disposed between the first and the second source/drain regions, and a gate electrode electrically insulated from the channel and adapted to control the conductivity of the channel. The access transistor is at least partially formed in the semiconductor substrate. The storage capacitor is adapted to be accessed by the access transistor. The storage capacitor includes at least first and second storage electrodes and at least a capacitor dielectric disposed between the first and the second storage electrodes. Each of the first and the second storage electrodes is disposed above the substrate surface.
摘要翻译：存储器件包括存储单元阵列和用于存储信息的存储电容器。每个存储单元包括存取晶体管。存取晶体管包括第一和第二源极/漏极区域，设置在第一和第二源极/漏极区域之间的沟道以及与沟道电绝缘并适于控制沟道的导电性的栅电极。存取晶体管至少部分地形成在半导体衬底中。存储电容适于由存取晶体管访问。存储电容器至少包括第一和第二存储电极以及设置在第一和第二存储电极之间的至少一个电容器电介质。第一和第二存储电极中的每一个设置在基板表面上方。

9. 发明申请

US20100090264A1 INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US20100090264A1
公开(公告)日：2010-04-15
申请号：US12249060
申请日：2008-10-10
申请人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
发明人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。互连件包括布置在半导体本体表面下方的金属体。接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。还公开了其它方法，装置和系统。

10. 发明申请

US20100027325A1 INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD 有权
标题翻译：集成电路，包括记忆细胞阵列和方法
公开(公告)号：US20100027325A1
公开(公告)日：2010-02-04
申请号：US12182698
申请日：2008-07-30
申请人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： G11C11/00 , H01L21/00 , G11C11/34
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/24
摘要： An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.
摘要翻译：一种包括存储单元阵列和方法的集成电路。在一个实施例中，每个存储单元包括电阻切换存储器元件和用于从多个存储器单元中选择一个单元的选择二极管。存储元件与其顶部耦合到第一选择线并且其底侧连接到选择二极管，二极管还耦合到第二选择线的底侧。

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