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1. 发明授权

US07844798B2 Command protocol for integrated circuits 有权
标题翻译：集成电路命令协议
公开(公告)号：US07844798B2
公开(公告)日：2010-11-30
申请号：US11955659
申请日：2007-12-13
申请人： Andreas Gärtner , Georg Braun , Maurizio Skerlj , Johannes Stecker
发明人： Andreas Gärtner , Georg Braun , Maurizio Skerlj , Johannes Stecker
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C8/12 , G11C2207/2227 , Y02D10/14 , Y02D10/171
摘要： A method of operating an integrated circuit involves supplying an instruction portion of a command to the integrated circuit to specify an operation to be performed by the integrated circuit. At least some types of commands also include an attributes portion that provides additional information about the operation to be performed. The attributes portion of the command is supplied to the integrated circuit with a delay relative to the instruction portion of the command. The integrated circuit selectively enables circuitry for processing the attributes portion if the integrated circuit determines from the received instruction portion that the command also includes an attributes portion. The delay between the two portions of the command provides sufficient time for the integrated circuit to enable the attributes processing circuitry, which, in a default state, can be disabled during an active mode of the integrated circuit to save power.
摘要翻译：一种操作集成电路的方法包括向集成电路提供命令的指令部分，以指定要由集成电路执行的操作。至少一些类型的命令还包括提供关于要执行的操作的附加信息的属性部分。命令的属性部分相对于命令的指令部分延迟地提供给集成电路。如果集成电路从接收到的指令部分确定该命令还包括属性部分，则集成电路选择性地启用用于处理属性部分的电路。该命令的两个部分之间的延迟为集成电路提供了足够的时间，使得能够在集成电路的活动模式期间在默认状态下禁用属性处理电路以节省功率。

2. 发明授权

US07532523B2 Memory chip with settable termination resistance circuit 有权
标题翻译：内存芯片，可设置终端电阻电路
公开(公告)号：US07532523B2
公开(公告)日：2009-05-12
申请号：US11461380
申请日：2006-07-31
申请人： Georg Braun , Christian Weis , Eckehard Plaettner
发明人： Georg Braun , Christian Weis , Eckehard Plaettner
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G06F13/4086 , G11C5/04
摘要： Methods and apparatus for setting various terminations of a memory chip. The memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.
摘要翻译：用于设置存储芯片的各种终端的方法和装置。存储器芯片包括终端，可以连接到终端以终止具有可设置电阻值的终端的终端电路，用于接收控制命令信号的控制命令端口以及连接到终端的控制电路电路，以便根据接收到的控制命令信号设置电阻值。

3. 发明授权

US07149864B2 Method and circuit for allocating memory arrangement addresses 有权
标题翻译：分配存储器配置地址的方法和电路
公开(公告)号：US07149864B2
公开(公告)日：2006-12-12
申请号：US10777992
申请日：2004-02-12
申请人： Georg Braun , Andreas Jakobs
发明人： Georg Braun , Andreas Jakobs
IPC分类号： G06F12/02
CPC分类号： G06F12/0669
摘要： Methods and apparatus for allocating memory arrangement addresses to a buffer chip, during an initialization mode, for use in addressing one or more memory arrangements connected to the buffer chip are provided. A buffer circuit may receive first initialization data specifying a first set of available memory arrangement addresses and associate one or more of the first set of available memory arrangement addresses with the one or more memory arrangements connected to the buffer chip. The buffer circuit may also generate second initialization data specifying the set of available memory arrangement addresses available after the association. The second initialization data may be transmitted to another buffer circuit for use in address allocation or back to a memory access control unit.
摘要翻译：提供了用于在初始化模式期间将存储器布置地址分配给缓冲器芯片用于寻址连接到缓冲器芯片的一个或多个存储器配置的方法和装置。缓冲器电路可以接收指定第一组可用存储器布置地址的第一初始化数据，并将第一组可用存储器配置地址中的一个或多个与连接到缓冲器芯片的一个或多个存储器配置相关联。缓冲电路还可以产生指定在关联之后可用的可用存储器布置地址的集合的第二初始化数据。第二初始化数据可以被发送到用于地址分配的另一缓冲电路或者返回到存储器访问控制单元。

4. 发明申请

US20060262613A1 Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted 有权
标题翻译：半导体存储器和方法，用于在接收要发送的写入数据期间适配时钟信号和选通信号之间的相位关系
公开(公告)号：US20060262613A1
公开(公告)日：2006-11-23
申请号：US11410320
申请日：2006-04-24
申请人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
发明人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.
摘要翻译：提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

5. 发明授权

US07139290B2 Transmitting data into a memory cell array 有权
公开(公告)号：US07139290B2
公开(公告)日：2006-11-21
申请号：US10171098
申请日：2002-06-13
申请人： Georg Braun
发明人： Georg Braun
IPC分类号： H04J3/08 , G11C8/00
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1078
摘要： A method for transmitting a data stream from a circuit unit to a memory cell array includes receiving the data stream and demultiplexing it in response to a control signal, thereby dividing the data stream into a storage data stream and a mask data stream. The storage data stream is then buffered into a register unit, where it is divided into data stream components buffered in corresponding data register components on the basis of a clock signal and an address signal provided to the register unit. Meanwhile, the mask data stream is buffered in a mask register of the register unit. A composite data stream is then formed by combining selected data stream components in response to information provided by a data mask unit from the mask data stream buffered in the mask register. Data corresponding to this composite data stream is then provided to the memory cell array for storage therein.

6. 发明授权

US07127553B2 Method for determining the optimum access strategy 有权
标题翻译：确定最佳访问策略的方法
公开(公告)号：US07127553B2
公开(公告)日：2006-10-24
申请号：US10717337
申请日：2003-11-19
申请人： Alexander Benedix , Georg Braun , Bernd Klehn
发明人： Alexander Benedix , Georg Braun , Bernd Klehn
IPC分类号： H01L27/108
CPC分类号： G06F11/3409
摘要： A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.
摘要翻译：用于执行数据处理过程的配置具有由操作系统使用用于执行系统进程的访问策略来访问的操作系统和各种系统资源。当有不同的应用程序时，使用与系统资源不同的访问策略。还提供了一种用于确定对系统资源的最佳访问策略的方法。

7. 发明授权

US06894330B2 Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor 失效
标题翻译：用于从铁电晶体管中读取状态并存储状态的存储器配置和方法
公开(公告)号：US06894330B2
公开(公告)日：2005-05-17
申请号：US09783187
申请日：2001-02-14
申请人： Harald Bachhofer , Georg Braun , Thomas Peter Haneder , Wolfgang Hönlein , Marc Ullmann
发明人： Harald Bachhofer , Georg Braun , Thomas Peter Haneder , Wolfgang Hönlein , Marc Ullmann
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： G11C11/22
摘要： The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.
摘要翻译：读取或存储存储单元中的铁电晶体管的状态，并且在读取或存储期间在存储矩阵中的另外的存储单元中的另外的铁电晶体管的阈值电压增加或永久地增加。还提供了包括铁电存储单元的存储器配置。

8. 发明授权

US06697279B2 Ferroelectric read/write memory with series-connected memory cells (CFRAM) 失效
标题翻译：具有串联存储单元（CFRAM）的铁电读/写存储器
公开(公告)号：US06697279B2
公开(公告)日：2004-02-24
申请号：US09758300
申请日：2001-01-10
申请人： Ronny Schneider , Georg Braun
发明人： Ronny Schneider , Georg Braun
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： The memory device has series-connected ferroelectric memory cells in which a series circuit composed of a resistor and/or of a transistor for the ferroelectric capacitor of a respective memory cell is present. As a result, without unacceptably increasing the access time, the interference pulses at the ferroelectric capacitors of the memory cells which are not being addressed at that particular time and which are generated by the reading out or writing of the addressed memory cell are reduced in such a way that they have virtually no further influence on the non-addressed memory cells.
摘要翻译：存储器件具有串联连接的铁电存储器单元，其中存在由相应存储单元的铁电电容器的电阻器和/或晶体管组成的串联电路。结果是，在没有不可接受地增加访问时间的情况下，在特定时间没有被寻址并且通过寻址的存储器单元的读出或写入而产生的存储单元的铁电电容器处的干扰脉冲被减少它们对于非寻址存储器单元几乎没有进一步的影响。

9. 发明授权

US06500677B2 Method for fabricating a ferroelectric memory configuration 失效
标题翻译：铁电存储器配置的制造方法
公开(公告)号：US06500677B2
公开(公告)日：2002-12-31
申请号：US10027106
申请日：2001-12-26
申请人： Renate Bergmann , Christine Dehm , Thomas Roehr , Georg Braun , Heinz Hoenigschmid , Günther Schindler
发明人： Renate Bergmann , Christine Dehm , Thomas Roehr , Georg Braun , Heinz Hoenigschmid , Günther Schindler
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L27/11507
摘要： The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a multiplicity of memory cells. Each of the memory cells has at least one select transistor, at least one short-circuit transistor, and at least one ferroelectric capacitor. The transistors are connected in an electrically conductive manner to a first of the electrodes of the ferroelectric capacitor. In the next step, at least one electrically insulating layer is applied. In the next step, at least one contact hole for connecting a second electrode of the ferroelectric capacitors is produced. Next, contact holes for connecting the short-circuit transistors are produced. Next, the contact holes are filled with electrically conductive material. Next, an electrically conductive layer is applied and patterned, so that the second electrodes of the ferroelectric capacitors are each conductively connected to the short-circuit transistors.
摘要翻译：本发明提供了一种方法。在制造铁电存储器结构的方法的第一步骤中，提供了具有多个存储单元的衬底。每个存储单元具有至少一个选择晶体管，至少一个短路晶体管和至少一个铁电电容器。晶体管以导电方式连接到铁电电容器的第一电极。在下一步骤中，施加至少一个电绝缘层。在下一步骤中，产生用于连接铁电电容器的第二电极的至少一个接触孔。接下来，制造用于连接短路晶体管的接触孔。接下来，接触孔填充有导电材料。接下来，施加导电层并图案化，使得强电介质电容器的第二电极分别与短路晶体管导通。

10. 发明授权

US06487128B2 Integrated memory having memory cells and reference cells, and operating method for such a memory 有权
标题翻译：具有存储单元和参考单元的集成存储器以及用于这种存储器的操作方法
公开(公告)号：US06487128B2
公开(公告)日：2002-11-26
申请号：US09962411
申请日：2001-09-24
申请人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
发明人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/14
摘要： The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.
摘要翻译：存储器具有相同构造的存储器单元和参考单元。通过经由第一开关元件将读取放大器的参考单元解耦，并且经由第二开关元件将连接到参考单元的位线的一部分电连接到电位线，将参考信息项写入参考单元携带参考信息。

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