专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US08144531B2 Latency control circuit, semiconductor memory device including the same, and method for controlling latency 失效
标题翻译：延迟控制电路，包括其的半导体存储器件以及用于控制延迟的方法
公开(公告)号：US08144531B2
公开(公告)日：2012-03-27
申请号：US12633387
申请日：2009-12-08
申请人： Hae-Rang Choi , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hae-Rang Choi , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2272
摘要： A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.
摘要翻译：延迟控制电路包括路径计算器，被配置为计算输入信号在芯片内经过的路径的延迟值，并输出延迟值作为路径信息;延迟值计算器，被配置为输出表示延迟值的延迟信息用于基于所述输入信号和所述路径信息的等待时间值延迟所述输入信号;以及延迟器，被配置为将所述输入信号延迟与所述延迟信息相对应的延迟。

72. 发明授权

US08120442B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08120442B2
公开(公告)日：2012-02-21
申请号：US12266787
申请日：2008-11-07
申请人： Ji-Wang Lee , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
发明人： Ji-Wang Lee , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
IPC分类号： H04B3/04
CPC分类号： H04B3/32 , H03K5/131 , H03K5/135 , H03K5/1534 , H03K2005/00071 , H04L25/0272 , H04L25/0286 , H04L25/029
摘要： A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units.
摘要翻译：半导体器件包括用于传送信号的传输线和转换检测器，每个传输线检查多条传输线中的每条传输线上的传输信号是否被转换。如果信号被转移，则检测其转换形状。信号模式确定单元响应于来自多个转换检测器的输出信号来确定相邻传输线之间的信号传输模式。延迟单元耦合到各个传输线，用于根据来自信号模式确定单元的相应输出信号来调整传输信号的传输延迟。

73. 发明授权

US08076964B2 Sampling circuit 有权
标题翻译：采样电路
公开(公告)号：US08076964B2
公开(公告)日：2011-12-13
申请号：US12630021
申请日：2009-12-03
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K3/00
CPC分类号： H03K3/356139 , G06F5/06 , H03K3/0375
摘要： A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.
摘要翻译：一种用于半导体器件的采样电路，包括：第一采样单元，被配置为与参考时钟信号同步地采样数据信号并输出第一输出信号;第二采样单元，被配置为与延迟数据信号同步采样参考时钟信号并输出第二输出信号;以及输出单元，被配置为组合第一和第二输出信号并输出采样数据信号。

74. 发明申请

US20110285419A1 SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS 审中-公开
标题翻译：用于产生时钟信号的半导体集成电路
公开(公告)号：US20110285419A1
公开(公告)日：2011-11-24
申请号：US13204594
申请日：2011-08-05
申请人： Hyung Soo Kim , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
发明人： Hyung Soo Kim , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G01R29/26
摘要： A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference dock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
摘要翻译：一种用于半导体集成电路的电压测量装置包括：第一延迟单元，被配置为延迟第一区域中的参考时钟;第二延迟单元，被配置为在第二区域中延迟参考基准;以及分析单元，被配置为分析电压差基于与由第一延迟单元和第二延迟单元产生的延迟时钟信号相关联的相位，区域之间的电平。

75. 发明授权

US08040303B2 Organic light emitting display 有权
标题翻译：有机发光显示器
公开(公告)号：US08040303B2
公开(公告)日：2011-10-18
申请号：US11790656
申请日：2007-04-26
申请人： Hyung-Soo Kim , Wang-Jo Lee , Bo-Yong Chung , Sang-Moo Choi
发明人： Hyung-Soo Kim , Wang-Jo Lee , Bo-Yong Chung , Sang-Moo Choi
IPC分类号： G09G3/32
CPC分类号： G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2310/0251
摘要： An organic light emitting display, suitable for a high quality and high resolution display device, rapidly charges a data voltage using a voltage programming technique, after compensating for a deviations in the threshold voltage and mobility of a driving transistor using a current programming technique. The organic light emitting display includes: a data line supplying a data signal; a scan line supplying a scan signal; a first switching element, electrically coupling its control electrode to the scan line, transferring the data signal supplied from the data line; a driving transistor, electrically coupling its control electrode to the first switching element, controlling a driving current of a first voltage line; a first capacitive element electrically coupled between the first switching element and the control electrode of the driving transistor; an Organic Light Emitting Diode (OLED), electrically coupled between the driving transistor and a second power voltage line, displaying an image by a current supplied from the driving transistor; and a fourth switching element compensating for deviations of characteristics of the driving transistor by supplying a current of the first current line to the driving transistor.
摘要翻译：在使用当前编程技术补偿驱动晶体管的阈值电压和迁移率的偏差之后，适用于高质量和高分辨率的显示装置的有机发光显示器使用电压编程技术快速充电数据电压。有机发光显示器包括：提供数据信号的数据线; 提供扫描信号的扫描线; 第一开关元件，将其控制电极电耦合到扫描线，传送从数据线提供的数据信号; 驱动晶体管，将其控制电极电耦合到第一开关元件，控制第一电压线的驱动电流; 电耦合在第一开关元件和驱动晶体管的控制电极之间的第一电容元件; 电耦合在驱动晶体管和第二电源电压线之间的有机发光二极管（OLED），通过从驱动晶体管提供的电流显示图像; 以及第四开关元件，通过将所述第一电流线的电流提供给所述驱动晶体管来补偿所述驱动晶体管的特性的偏差。

76. 发明授权

US08033481B2 Structure for fixing reducer for sprinkler in side wall 有权
公开(公告)号：US08033481B2
公开(公告)日：2011-10-11
申请号：US12460549
申请日：2009-07-20
申请人： Hyung Soo Kim
发明人： Hyung Soo Kim
IPC分类号： B05B15/10
CPC分类号： F16L3/18 , A62C31/28 , A62C35/68
摘要： The present invention relates to a structure for fixing a reducer for a sprinkler in a side wall, and more particularly, to a structure for fixing a reducer for a sprinkler for side wall construction, in which since the reducer can easily adjust a distance from the side wall in the horizontal direction, a connection work between the reducer and the sprinkler head for the side wall construction connected to the reducer can be conveniently performed.

77. 发明授权

US07952394B2 Signal receiver circuit capable of improving area and power efficiency in semiconductor integrated circuits 有权
标题翻译：信号接收电路能够提高半导体集成电路的面积和功率效率
公开(公告)号：US07952394B2
公开(公告)日：2011-05-31
申请号：US12770706
申请日：2010-04-29
申请人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03K5/22
CPC分类号： H03K5/08 , H03K3/356139 , H03K3/356191 , H04L25/062
摘要： A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.
摘要翻译：信号接收器电路包括第一电平检测器，用于响应于一对第一参考信号偏移控制第一输出节点。第二级检测器偏移 - 响应于一对第二参考信号来控制第二输出节点。

78. 发明授权

US07948287B2 DLL circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的DLL电路
公开(公告)号：US07948287B2
公开(公告)日：2011-05-24
申请号：US11964824
申请日：2007-12-27
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.
摘要翻译：一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。

79. 发明申请

US20110058433A1 LATENCY CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR CONTROLLING LATENCY 失效
标题翻译：延迟控制电路，包括其的半导体存储器件以及控制延迟的方法
公开(公告)号：US20110058433A1
公开(公告)日：2011-03-10
申请号：US12633387
申请日：2009-12-08
申请人： Hae-Rang Choi , Yong-ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hae-Rang Choi , Yong-ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/22 , H03L7/00
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2272
摘要： A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.
摘要翻译：延迟控制电路包括路径计算器，被配置为计算输入信号在芯片内经过的路径的延迟值，并输出延迟值作为路径信息;延迟值计算器，被配置为输出表示延迟值的延迟信息用于基于所述输入信号和所述路径信息的等待时间值延迟所述输入信号;以及延迟器，被配置为将所述输入信号延迟与所述延迟信息相对应的延迟。

80. 发明申请

US20110001533A1 SAMPLING CIRCUIT 有权
标题翻译：采样电路
公开(公告)号：US20110001533A1
公开(公告)日：2011-01-06
申请号：US12630021
申请日：2009-12-03
申请人： Ji-Wang LEE , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang LEE , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K3/00 , G06F7/42 , G06G7/12
CPC分类号： H03K3/356139 , G06F5/06 , H03K3/0375
摘要： A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.
摘要翻译：一种用于半导体器件的采样电路，包括：第一采样单元，被配置为与参考时钟信号同步地采样数据信号并输出第一输出信号;第二采样单元，被配置为与延迟数据信号同步采样参考时钟信号并输出第二输出信号，以及输出单元，被配置为组合第一和第二输出信号并输出采样数据信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式