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    • 71. 发明申请
      US20090259869A1 SAMPLING CHIP ACTIVITY FOR REAL TIME POWER ESTIMATION 有权
    • SAMPLING CHIP ACTIVITY FOR REAL TIME POWER ESTIMATION
    • 采样切片活动实时功率估计
    • US20090259869A1
    • 2009-10-15
    • US12101598
    • 2008-04-11
    • Samuel D. Naffziger
    • Samuel D. Naffziger
    • G06F11/30 , G06F1/26
    • G06F1/3203 , G06F1/26 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
    • A system and method for real-time power estimation. A core may be divided into units. Each unit is simulated to achieve a real power consumption characterization. The power consumption is sampled. Statistical analysis is performed that assumes the core has node capacitance switching behavior that is approximated by a stationary random process with a Poisson distribution. The statistical analysis determines the number of samples to take during a sample interval. The operational frequency, sample interval, and number of samples are used to determine the number of signals to sample. Signals are chosen that have a high correlation with the node capacitance switching behavior, such as clock enable signals on the last stage of a clock distribution system. Weights with tuned values are assigned to each sampled signal. Sampling occurs during every predetermined number of clock cycles. The weights of asserted sampled signals are summed in order to determine a repeatable power estimation value.
    • 一种用于实时功率估计的系统和方法。 核心可分为单位。 模拟每个单元以实现真正的功耗表征。 对功耗进行采样。 执行统计分析，假定核心具有由具有泊松分布的静态随机过程近似的节点电容切换行为。 统计分析确定在采样间隔期间采样的数量。 使用操作频率，采样间隔和采样数量来确定采样信号的数量。 选择与节点电容切换行为高度相关的信号，例如时钟分配系统的最后阶段的时钟使能信号。 具有调谐值的重量被分配给每个采样信号。 在每个预定数量的时钟周期内进行采样。 所确定的采样信号的权重被相加以便确定可重复的功率估计值。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 72. 发明申请
      US20090256609A1 LOW POWER FLIP FLOP THROUGH PARTIALLY GATED SLAVE CLOCK 有权
    • LOW POWER FLIP FLOP THROUGH PARTIALLY GATED SLAVE CLOCK
    • 低功率翻转通过部分门控时钟
    • US20090256609A1
    • 2009-10-15
    • US12100040
    • 2008-04-09
    • Samuel D. Naffziger
    • Samuel D. Naffziger
    • H03K3/289 , H03K3/00 , H03K3/356
    • H03K3/35625 , H03K3/012 , H03K5/135
    • A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived from an ungated input clock signal and a clock gating condition. The clock gating condition determines when an input data signal of the flip-flop and the stored internal state of the slave latch have the same logic value, such as only a logic low value. If they have the same value, toggling of the ungated input clock signal is not received by the slave latch, signal switching of internal nodes of the slave latch is reduced, and power consumption is reduced.
    • 一种用于降低半导体芯片上的触发器电路内的功耗的系统和方法。 门锁输入时钟信号由从锁存器接收。 门控输入时钟源自非门控输入时钟信号和时钟门控条件。 时钟门控条件确定触发器的输入数据信号和从锁存器的存储内部状态何时具有相同的逻辑值，例如仅逻辑低电平值。 如果它们具有相同的值，则从锁存器不接收到非门控输入时钟信号的切换，从锁存器的内部节点的信号切换被减少，并且功耗降低。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 75. 发明授权
      US06549605B1 Limiting loss in a circuit 失效
    • Limiting loss in a circuit
    • 限制电路损耗
    • US06549605B1
    • 2003-04-15
    • US10171233
    • 2002-06-14
    • Samuel D. Naffziger , Don Douglas Josephson
    • Samuel D. Naffziger , Don Douglas Josephson
    • G11C1900
    • H03K5/06 , H03K19/00346 , H03K19/096
    • A circuit for limiting loss in a second circuit. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reaches a first predetermined amount of time, where the first predetermined amount of time is related to a parameter of the second circuit. The second timer may produce a second output in the given state if the first timer does not produce the first output in the given state when the duration of the pulse reaches a second predetermined amount of time. The one or more logic gates may have an output that is the same as the pulse unless and until the output of the first timer or the second timer is in the given state, at which time, the output of the one or more logic gates is forced to a non-pulsed state.
    • 用于限制第二电路中的损耗的电路。 电路可以包括第一定时器，第二定时器和一个或多个逻辑门。 如果与第二电路一起使用的脉冲的持续时间达到第一预定时间量，则第一定时器可以在给定状态下产生第一输出，其中第一预定时间量与第二电路的参数相关。 如果当脉冲持续时间达到第二预定时间量时，如果第一定时器在给定状态下不产生第一输出，则第二定时器可以在给定状态下产生第二输出。 一个或多个逻辑门可以具有与脉冲相同的输出，除非和直到第一定时器或第二定时器的输出处于给定状态，此时一个或多个逻辑门的输出为 被迫进入非脉冲状态。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 76. 发明授权
      US06489834B2 System and method utilizing on-chip voltage monitoring to manage power consumption 有权
    • System and method utilizing on-chip voltage monitoring to manage power consumption
    • 利用片上电压监控的系统和方法来管理功耗
    • US06489834B2
    • 2002-12-03
    • US09811243
    • 2001-03-16
    • Samuel D. Naffziger , Don D Josephson
    • Samuel D. Naffziger , Don D Josephson
    • H03K301
    • G06F1/32 , G01R31/2843 , H02J1/14
    • A system and method are disclosed that utilize analog detection of an integrated circuit's (“chip's”) power consumption to enable power consumption management. On-chip circuitry may be utilized to detect analog electrical characteristics of the chip, such as its voltage, from which the chip's power consumption is determined. One embodiment utilizes on-chip circuitry to manage long-term, sustained power consumption of the chip, which encompasses power consumption for approximately a microsecond, as well as more extended time frames. Another embodiment utilizes on-chip circuitry to manage short-term power consumption of the chip, which encompasses power consumption for less than a microsecond (e.g., nanosecond time frame). A preferred embodiment implements both the circuitry for managing long-term power consumption and the circuitry for managing short-term power consumption. On-chip control circuitry may be implemented to trigger certain operations to reduce the chip's long-term and/or short-term power consumption upon determination that such power consumption is too high.
    • 公开了利用集成电路（“芯片”）功耗的模拟检测来实现功耗管理的系统和方法。 片上电路可以用于检测芯片的模拟电气特性，例如其电压，确定芯片的功耗。 一个实施例利用片上电路来管理芯片的长期，持续的功耗，其包括大约一微秒的功率消耗以及更长的时间帧。 另一实施例利用片上电路来管理芯片的短期功耗，其包括小于一微秒（例如，纳秒时间帧）的功耗。 优选实施例同时实现用于管理长期功耗的电路和用于管理短期功耗的电路。 可以实现片上控制电路以在确定这种功率消耗太高时触发某些操作来减少芯片的长期和/或短期功耗。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 77. 发明授权
      US06448837B1 Reduced current variability I/O bus termination 失效
    • Reduced current variability I/O bus termination
    • 降低电流变化I / O总线终端
    • US06448837B1
    • 2002-09-10
    • US09754667
    • 2001-01-04
    • Samuel D. Naffziger
    • Samuel D. Naffziger
    • H03K508
    • H04L25/0298
    • A shunt and shunt control circuit are connected to the wires of an on-chip terminated I/O bus. Each instance monitors the wire that it is connected to. If the wire has been pulled low by any device on the bus, the circuit does nothing. If, however, the wire was not pulled low, then current is shunted from the termination voltage supply to ground. The turn on and turn off rates for this shunt are matched to the ramps of current through the termination impedance of the bus. This makes the variability in current drawn from the termination voltage supply less data dependent.
    • 分路和分流控制电路连接到片上终止的I / O总线的导线。 每个实例都监视连接到的电线。 如果通过总线上的任何设备将电线拉低，该电路什么都不做。 然而，如果电线未拉低，则电流从端接电源分流到地。 该分流器的导通和关断速率与通过总线终端阻抗的电流斜坡匹配。 这使得从终端电压提供的电流的变化性较少取决于数据。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 80. 发明授权
      US6014732A Cache memory with reduced access time 失效
    • Cache memory with reduced access time
    • 具有减少访问时间的缓存内存
    • US6014732A
    • 2000-01-11
    • US955821
    • 1997-10-22
    • Samuel D. Naffziger
    • Samuel D. Naffziger
    • G06F12/08 , G06F12/10
    • G06F12/1045 , G06F12/0864 , G06F12/1054 , G06F2212/652
    • A cache with a translation lookaside buffer (TLB) that eliminates the need for retrieval of a physical address tag from the TLB when accessing the cache. The TLB includes two content addressable memories (CAM's). For each new cache line, in the tag portion of the cache, instead of storing physical tags, the cache stores vectors called physical hit vectors. Physical hit vectors are generated by a first TLB CAM. Each physical hit vector indicates all locations in the first TLB CAM containing the physical tag of the cache line. For a cache access, a second TLB CAM receives a virtual tag and generates a vector called a virtual hit vector. The virtual hit vector indicates the location in the second TLB CAM of the corresponding virtual tag. Then, instead of retrieving and comparing physical tags, the cache compares a virtual hit vector to a set of physical hit vectors without having to retrieve a physical tag. As a result, one operation is eliminated from a time critical path, reducing the access time. For caches having variable page sizes, an additional CAM structure stores page offset bits and corresponding bit masks from the operating system. Page offset bits are then used to further qualify comparison of virtual hit vectors and physical hit vectors.
    • 具有翻译后备缓冲器（TLB）的缓存，消除了在访问高速缓存时从TLB检索物理地址标签的需要。 TLB包括两个内容可寻址存储器（CAM）。 对于每个新的高速缓存行，在缓存的标签部分中，高速缓存存储物理标记，而不是存储物理标记，存储称为物理命中向量的向量。 物理撞击矢量由第一TLB CAM产生。 每个物理命中矢量指示包含高速缓存行的物理标记的第一TLB CAM中的所有位置。 对于高速缓存访​​问，第二TLB CAM接收虚拟标签并生成称为虚拟命中向量的向量。 虚拟命中向量表示相应虚拟标签的第二TLB CAM中的位置。 然后，高速缓存将虚拟命中向量与一组物理命中矢量进行比较，而不用检索和比较物理标签，而不用检索物理标签。 因此，从时间关键路径消除一个操作，减少访问时间。 对于具有可变页面大小的高速缓存，附加的CAM结构存储来自操作系统的页偏移位和对应的位掩码。 然后使用页面偏移位来进一步限定虚拟命中矢量和物理命中矢量的比较。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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