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71. 发明授权

US07659838B2 Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
公开(公告)号：US07659838B2
公开(公告)日：2010-02-09
申请号：US11359273
申请日：2006-02-21
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串器电路包括用于将串行数据转换成具有若干数据宽度的并行数据的电路。电路也可以在宽频率范围内的任何频率下工作。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

72. 发明授权

US07276936B1 Clock circuitry for programmable logic devices 有权
标题翻译：可编程逻辑器件的时钟电路
公开(公告)号：US07276936B1
公开(公告)日：2007-10-02
申请号：US11239702
申请日：2005-09-29
申请人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , In Whan Kim , Thungoc Tran
发明人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , In Whan Kim , Thungoc Tran
IPC分类号： H03K19/00
CPC分类号： H03K19/1774 , H03K19/17744
摘要： A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.
摘要翻译：可编程逻辑器件包括采用一个或多个时钟信号的高速串行接口（“HSSI”）电路。除了在HSSI电路中使用这些时钟信号之外，提供电路以允许这些信号中的至少一个分布在整个PLD核心电路中，例如用作PLD核心中的附加时钟信号。时钟分布优选以低偏斜方式进行。

73. 发明授权

US08222967B1 Receiver equalizer circuitry having wide data rate and input common mode voltage ranges 有权
标题翻译：接收机均衡器电路具有宽数据速率和输入共模电压范围
公开(公告)号：US08222967B1
公开(公告)日：2012-07-17
申请号：US12644128
申请日：2009-12-22
申请人： Sangeeta Raman , Tim Tri Hoang , Sergey Yuryevich Shumarayev
发明人： Sangeeta Raman , Tim Tri Hoang , Sergey Yuryevich Shumarayev
IPC分类号： H03H7/30 , H03F3/45
CPC分类号： H03F3/45192 , H03F3/193 , H03F3/45197 , H03F3/45475 , H03F3/72 , H03F2200/405 , H03F2203/45488 , H03F2203/45494 , H03F2203/45686 , H03F2203/7236 , H03H11/1213 , H03H11/48
摘要： Equalizer circuitry on an integrated circuit (“IC”) includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.
摘要翻译：集成电路（“IC”）上的均衡器电路包括串联连接的多个NMOS均衡器级。每个NMOS级可包括折叠的有源电感电路。每个NMOS级还可以包括具有可控制的可变电路参数的各种电路元件，使得均衡器可被可控地适用于执行宽范围的高速串行数据信号比特率和通信协议和/或通信条件的其它变化。例如，每个NMOS级可以是可编程的，以控制均衡器电路的带宽和功耗中的至少一个。在均衡的输入信号的电压对于初始NMOS级来说太低的情况下，均衡器也可以具有第一PMOS级，而不用第一NMOS级。

74. 发明申请

US20120063556A1 Techniques for Varying a Periodic Signal Based on Changes in a Data Rate 有权
标题翻译：基于数据速率变化的周期性信号变化技术
公开(公告)号：US20120063556A1
公开(公告)日：2012-03-15
申请号：US12881160
申请日：2010-09-13
申请人： Tim Tri Hoang
发明人： Tim Tri Hoang
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/087 , H03L7/183
摘要： A circuit includes a phase detection circuit, a phase adjustment circuit, and a sampler circuit. The phase detection circuit compares a phase of a first periodic signal to a phase of a second periodic signal to generate a control signal. The phase adjustment circuit causes the phase of the second periodic signal and a phase of a third periodic signal to vary based on a variation in the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The circuit varies a frequency of the third periodic signal to correspond to changes in a data rate of the data signal between at least three different data rates that are based on at least three data transmission protocols.
摘要翻译：电路包括相位检测电路，相位调整电路和采样电路。相位检测电路将第一周期信号的相位与第二周期信号的相位进行比较，以产生控制信号。相位调整电路使得第二周期信号的相位和第三周期信号的相位根据控制信号的变化而变化。采样器电路对数据信号进行采样，以响应于第三周期信号产生采样数据信号。电路改变第三周期信号的频率以对应于基于至少三个数据传输协议的至少三个不同数据速率之间的数据信号的数据速率的变化。

75. 发明授权

US07602255B1 Loop circuits that reduce bandwidth variations 有权
标题翻译：减少带宽变化的环路电路
公开(公告)号：US07602255B1
公开(公告)日：2009-10-13
申请号：US11861144
申请日：2007-09-25
申请人： Kang-Wei Lai , Ninh D. Ngo , Kazi Asaduzzaman , Mian Z. Smith , Wanli Chang , Tim Tri Hoang
发明人： Kang-Wei Lai , Ninh D. Ngo , Kazi Asaduzzaman , Mian Z. Smith , Wanli Chang , Tim Tri Hoang
IPC分类号： H03L7/00
CPC分类号： H03L7/0895 , H03L7/0812
摘要： A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.
摘要翻译：在集成电路上的反馈回路（例如锁相环）具有检测器，电荷泵和环路滤波器。电荷泵响应于集成电路的过程中的变化来调节其输出电流，以减少环路带宽的变化。电荷泵还响应于环路滤波器中的电阻器的电阻的变化来调整其输出电流，以减少环路带宽的变化。电荷泵还可以响应于集成电路的温度变化来调节其输出电流，以减少环路带宽的变化。集成电路上的延迟锁定环路具有相位检测器和电荷泵。电荷泵响应于集成电路的温度和过程的变化来调整其输出电流，以减少环路带宽的变化。

76. 发明授权

US08816745B1 Equalizer circuitry including both inductor based and non-inductor based equalizer stages 有权
标题翻译：均衡器电路包括基于电感和非电感的均衡器级
公开(公告)号：US08816745B1
公开(公告)日：2014-08-26
申请号：US13316361
申请日：2011-12-09
申请人： Sangeeta Raman , Tim Tri Hoang
发明人： Sangeeta Raman , Tim Tri Hoang
IPC分类号： H03L5/00
CPC分类号： H04L25/03878 , H03K19/018507
摘要： An equalizer circuitry that includes both inductor based and non-inductor based equalizer stages is provided. In one implementation, the equalizer circuitry includes a first equalizer circuitry including a first inductor based equalizer stage and a first non-inductor based equalizer stage coupled to the first inductor based equalizer stage. In one implementation, the equalizer circuitry further includes a second equalizer circuitry including a plurality of inductor based equalizer stages, where the plurality of inductor based equalizer stages includes the first inductor based equalizer stage. In one implementation, the first equalizer circuitry further includes a second inductor based equalizer stage coupled to the first inductor based equalizer stage and the first non-inductor based equalize stage.
摘要翻译：提供了包括基于电感器和非电感器的均衡器级的均衡器电路。在一个实现中，均衡器电路包括第一均衡器电路，其包括基于第一电感器的均衡器级和耦合到基于第一电感器的均衡器级的基于非电感器的第一非均衡器级。在一个实现中，均衡器电路还包括包括多个基于电感器的均衡器级的第二均衡器电路，其中多个基于电感器的均衡器级包括基于第一电感器的均衡器级。在一个实现中，第一均衡器电路还包括耦合到基于第一电感器的均衡器级和基于非电感器的第一非均衡级的基于第二电感器的均衡器级。

77. 发明授权

US08705605B1 Technique for providing loopback testing with single stage equalizer 有权
标题翻译：提供单级均衡器的环回测试技术
公开(公告)号：US08705605B1
公开(公告)日：2014-04-22
申请号：US13288701
申请日：2011-11-03
申请人： Sangeeta Raman , Tim Tri Hoang
发明人： Sangeeta Raman , Tim Tri Hoang
IPC分类号： H03K5/159 , H03H7/30 , H03H7/40
CPC分类号： H04L1/243 , H04B17/14 , H04L25/03878 , H04W52/0274 , Y02D70/00
摘要： Devices and methods for serial loopback testing in an integrated circuit (IC) are provided. To implement loopback testing, an equalizer stage of a receiver of the IC is powered down. In addition, the common-mode voltage of the equalizer stage is reduced and/or a bulk node of the equalizer stage is connected to ground. Doing so may reduce the impact of capacitive coupling from the input pins of buffer, thereby improving the quality of the loopback output signal.
摘要翻译：提供了集成电路（IC）中串行回送测试的设备和方法。为了实现环回测试，IC的接收机的均衡器级掉电。此外，均衡器级的共模电压被减小和/或均衡器级的体积节点连接到地。这样做可以减少来自缓冲器的输入引脚的电容耦合的影响，从而提高环回输出信号的质量。

78. 发明授权

US08188774B1 Apparatus and methods for activation of an interface on an integrated circuit 有权
标题翻译：用于激活集成电路上的接口的装置和方法
公开(公告)号：US08188774B1
公开(公告)日：2012-05-29
申请号：US12833718
申请日：2010-07-09
申请人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
发明人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
IPC分类号： H03L7/00
CPC分类号： H03K19/1774
摘要： One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.
摘要翻译：一个实施例涉及在集成电路的核心变得可操作时激活集成电路上的接口的方法。收发器通道的偏移校准由物理介质连接电路执行。传输频率被收发器通道的发射机锁相环锁定，并且接收频率被收发信机的接收机锁相环锁定。随后，当集成电路的核心部件变得可操作时，该接口被激活。另一实施例涉及包括收发信道电路，接口处理器和复位控制状态机的集成电路。另一实施例涉及包括复位控制状态机，收发信道电路，信道输入转向多路复用器和信道输出转向多路复用器的控制电路。还公开了其它实施例，方面和特征。

79. 发明授权

US08049532B1 Level shifter circuit with a thin gate oxide transistor 有权
标题翻译：具有薄栅极氧化物晶体管的电平移位电路
公开(公告)号：US08049532B1
公开(公告)日：2011-11-01
申请号：US12823596
申请日：2010-06-25
申请人： Simardeep Maangat , Vinh Van Ho , Tim Tri Hoang
发明人： Simardeep Maangat , Vinh Van Ho , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03L7/085 , H03K19/017509 , H03L7/087
摘要： A level shifting circuit with a thin gate transistor connected to the input of the output stage is presented. The level shifting circuit has an input stage that receives an input that is at first voltage. A transistor with a thin gate oxide has one terminal connected to the input stage and another terminal coupled to an input of the output stage. The output stage of the level shifting circuit is implemented with thick gate oxide transistors.
摘要翻译：提出了一种具有连接到输出级的输入端的薄栅极晶体管的电平移动电路。电平移位电路具有接收处于第一电压的输入的输入级。具有薄栅极氧化物的晶体管具有连接到输入级的一个端子和耦合到输出级的输入的另一个端子。电平移位电路的输出级由厚栅极氧化物晶体管实现。

80. 发明授权

US07656187B2 Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
标题翻译：用于可编程逻辑器件集成电路等的多通道通信电路
公开(公告)号：US07656187B2
公开(公告)日：2010-02-02
申请号：US11288810
申请日：2005-11-28
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang , Ning Xue , Chong Lee , Ramanand Venkata
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang , Ning Xue , Chong Lee , Ramanand Venkata
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作一起，八个渠道在一起等）。共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以便于诸如电路设计和验证之类的事情。

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