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71. 发明授权

US08831140B2 Protocol-agnostic automatic rate negotiation for high-speed serial interface in a programmable logic device 有权
标题翻译：可编程逻辑器件中高速串行接口的协议无关自动速率协商
公开(公告)号：US08831140B2
公开(公告)日：2014-09-09
申请号：US11687052
申请日：2007-03-16
申请人： Allen Chan , Wilson Wong , Sergey Shumarayev
发明人： Allen Chan , Wilson Wong , Sergey Shumarayev
IPC分类号： H04L27/00 , H03K19/177 , G06F13/38 , H04L5/14
CPC分类号： G06F13/385 , H03K19/177 , H03K19/17744 , H04L5/1446
摘要： Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.
摘要翻译：用于可编程逻辑器件中的高速串行接口的自动速率协商逻辑确定单个位转换的多次出现（即，从“0”到“1”到“0”或从“1”到“1”的数据转换 0“到”1“）发生在高速串行接口的数据信道上的预定时间间隔内。间隔优选地被选择为使得多次出现单位转换意味着数据信道以全速率模式运行。速率协商逻辑可以在接口中共享具有时钟数据恢复电路的相位检测器。相位检测器可以是专门用于检测单位转换的爆发相位检测器。

72. 发明授权

US08669828B1 Decoupling capacitor control circuitry 有权
标题翻译：去耦电容控制电路
公开(公告)号：US08669828B1
公开(公告)日：2014-03-11
申请号：US12909739
申请日：2010-10-21
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev
IPC分类号： H04B3/28
CPC分类号： H01L23/642 , H01L2924/0002 , H05K1/0231 , H01L2924/00
摘要： Integrated circuits with decoupling capacitor circuitry are provided. Decoupling capacitor circuitry may include multiple arrays of decoupling capacitors. Each decoupling capacitor array may have a corresponding decoupling capacitor monitoring circuit that is associated with that decoupling capacitor array. Each decoupling capacitor monitoring circuit may include a resistor and switching circuitry. Each decoupling capacitor monitoring circuit may be coupled to a comparator and control circuitry. During testing, the control circuitry may configure each decoupling capacitor array for leakage current testing one at a time. If a decoupling capacitor array is determined to exhibit excessive leakage currents, that decoupling capacitor array will be marked as defective and will be disabled from use. If the decoupling capacitor array is determined to exhibit tolerable leakage currents, that decoupling capacitor array will be enable for use to help reduce power supply noise.
摘要翻译：提供具有去耦电容电路的集成电路。去耦电容器电路可以包括多个去耦电容器阵列。每个去耦电容器阵列可以具有与该去耦电容器阵列相关联的相应的去耦电容器监控电路。每个去耦电容器监控电路可以包括电阻器和开关电路。每个去耦电容器监控电路可以耦合到比较器和控制电路。在测试期间，控制电路可以配置每个去耦电容器阵列以便一次一个地进行漏电流测试。如果解耦电容器阵列被确定为表现出过多的漏电流，则该去耦电容阵列将被标记为有缺陷的并且将被禁止使用。如果解耦电容器阵列被确定为表现出可容忍的漏电流，则该去耦电容器阵列将被用于帮助减少电源噪声。

73. 发明授权

US08111784B1 On-chip data signal eye monitoring circuitry and methods 有权
标题翻译：片上数据信号眼监测电路及方法
公开(公告)号：US08111784B1
公开(公告)日：2012-02-07
申请号：US12082483
申请日：2008-04-11
申请人： Weiqi Ding , Mingde Pan , Wilson Wong , Sergey Shumarayev , Peng Li
发明人： Weiqi Ding , Mingde Pan , Wilson Wong , Sergey Shumarayev , Peng Li
IPC分类号： H04L25/06
CPC分类号： H04L25/063
摘要： Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.
摘要翻译：用于收集关于高速串行数据信号的眼睛的信息的方法和装置包括在几个眼睛切片位置采样重复的多位数据模式的每一位。对于任何给定的眼片位置，将数据模式中的每个位在电压中与基线参考信号电压进行比较，以建立该位的参考值。然后在重复电压比较时，参考信号电压逐渐增加，直到比较结果的一些位与该位的参考值不同。这在眼部切片位置建立了眼睛的上限值。然后，参考信号电压逐渐减小，以类似地找到该眼片的较低值。

74. 发明申请

US20110211621A1 HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的宽范围可编程性的异构收发器架构
公开(公告)号：US20110211621A1
公开(公告)日：2011-09-01
申请号：US13103132
申请日：2011-05-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04L5/14 , H04L27/00
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

75. 发明授权

US07924184B1 High-speed serial interface circuitry for programmable integrated circuit devices 有权
标题翻译：用于可编程集成电路器件的高速串行接口电路
公开(公告)号：US07924184B1
公开(公告)日：2011-04-12
申请号：US11904008
申请日：2007-09-24
申请人： Allen Chan , Sergey Shumarayev , Wilson Wong
发明人： Allen Chan , Sergey Shumarayev , Wilson Wong
IPC分类号： H03M9/00
CPC分类号： H03K19/1732
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and a channel of high-speed serial data signal interface (e.g., transceiver) circuitry. To facilitate enabling the integrated circuit to support any of many possible different high-speed serial communication protocols, the channel is hard-wired to include a parallel data bus of fixed width for exchanging parallel data with the programmable circuitry. Regardless of the protocol being implemented, the full width of this bus is always used. A portion of the programmable circuitry is programmed to convert data between the block width and a group width, which can be different from the block width and which is used for the data elsewhere in the integrated circuit.
摘要翻译：集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和高速串行数据信号接口（例如，收发器）电路的通道。为了使集成电路能够支持许多可能的不同高速串行通信协议中的任何一种，该信道被硬接线以包括用于与可编程电路交换并行数据的固定宽度的并行数据总线。无论正在执行协议，始终使用该总线的全宽。可编程电路的一部分被编程为在块宽度和组宽度之间转换数据，其可以与块宽度不同，并且用于集成电路中其他地方的数据。

76. 发明授权

US07821343B1 Transmitter with multiple phase locked loops 有权
标题翻译：具有多个锁相环的变送器
公开(公告)号：US07821343B1
公开(公告)日：2010-10-26
申请号：US12229813
申请日：2008-08-27
申请人： Wilson Wong , Sergey Shumarayev , Allen Chan , Weiqi Ding
发明人： Wilson Wong , Sergey Shumarayev , Allen Chan , Weiqi Ding
IPC分类号： H03L7/00
CPC分类号： H03L7/23
摘要： A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.
摘要翻译：描述了包括耦合到第一PLL的第一锁相环（PLL）和第二PLL的发射机。在一个实现中，第一PLL是电感 - 电容（LC）型PLL，第二PLL是环型PLL。此外，在一个实施例中，发射机还包括耦合到第一和第二PLL的PLL选择多路复用器，其中PLL选择多路复用器接收第一PLL的输出和第二PLL的输出，并输出第一PLL的输出或第二PLL的输出。在一个实现中，用于控制PLL选择多路复用器的选择的控制信号在运行时可编程。在一个实现中，本发明的发射机还包括耦合到PLL选择多路复用器的时钟产生模块，耦合到时钟产生模块的串行器模块和耦合到串行器模块的发送驱动器模块。在一个实施例中，发射驱动器块仅包括一个抽头前驱动器和仅一个主抽头预驱动器。本发明的发射机能够通过选择适当的PLL在宽范围模式或低抖动模式下工作。在宽范围模式下，需要较宽的频率范围。另一方面，在低抖动模式中，需要低抖动。

77. 发明授权

US07773668B1 Adaptive equalization methods and apparatus for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的自适应均衡方法和装置
公开(公告)号：US07773668B1
公开(公告)日：2010-08-10
申请号：US10762864
申请日：2004-01-21
申请人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03044 , H04L2025/03356 , H04L2025/03579 , H04L2025/03783
摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.
摘要翻译：可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否（5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。

78. 发明授权

US07760799B2 Programmable digital equalization control circuitry and methods 失效
标题翻译：可编程数字均衡控制电路和方法
公开(公告)号：US07760799B2
公开(公告)日：2010-07-20
申请号：US11238365
申请日：2005-09-28
申请人： Tin H. Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
发明人： Tin H. Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H03G3/3089 , H04L25/03885
摘要： Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.
摘要翻译：均衡电路可用于补偿由传输介质引起的数据信号的衰减。用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级的控制输入。比较器可以确定来自均衡电路的增益是否小于或大于期望的增益量。可编程上/下计数器可以根据比较器的输出来调整计数器值。可以使用一个或多个数模转换器将计数器值转换成一个或多个模拟电压。这些模拟电压可以作为控制输入提供给均衡级。控制电路还可以包括滞后电路，当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。

79. 发明申请

US20100090774A1 Techniques For Providing Option Conductors to Connect Components in an Oscillator Circuit 有权
标题翻译：提供选项导体连接振荡器电路中组件的技术
公开(公告)号：US20100090774A1
公开(公告)日：2010-04-15
申请号：US12277810
申请日：2008-11-25
申请人： Sergey Shumarayev , Wilson Wong , Allen Chan , Ali Atesoglu
发明人： Sergey Shumarayev , Wilson Wong , Allen Chan , Ali Atesoglu
IPC分类号： H03B5/18
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1243 , H03B5/1265 , H03B2201/011
摘要： An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.
摘要翻译：振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。振荡器电路还包括第二导电层中的变容二极管，电容器和选项导体。选项导体形成晶体管之一和电容器或变容二极管之间的连接的至少一部分。

80. 发明申请

US20090285275A1 SIGNAL ADJUSTMENT RECEIVER CIRCUITRY 失效
标题翻译：信号调整接收机电路
公开(公告)号：US20090285275A1
公开(公告)日：2009-11-19
申请号：US12511022
申请日：2009-07-28
申请人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
发明人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
IPC分类号： H04L27/01
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。对于低频调整，控制块控制信号归一化块中的归一化信号幅度。以这种方式，在信号归一化块中执行低频内容的受控调整。

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