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71. 发明授权

US10003890B2 MEMS microphone 有权
公开(公告)号：US10003890B2
公开(公告)日：2018-06-19
申请号：US15119878
申请日：2015-06-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Yonggang Hu
IPC分类号： H04R19/04 , H04R7/14 , H04R7/12 , B81B3/00 , H04R7/16
CPC分类号： H04R19/04 , B81B3/0037 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , G01L9/0045 , G01L9/0073 , H04R7/12 , H04R7/14 , H04R7/16 , H04R19/005 , H04R2201/003
摘要： A MEMS microphone includes a substrate (100), a supporting part (200), an upper polar plate (300) and a lower polar plate (400). The substrate (100) is provided with an opening (120) penetrating the middle thereof; the lower polar plate (400) straddles the opening (120); the supporting part (200) is fixed on the lower polar plate (400); the upper polar plate (300) is affixed to the supporting part (200); an accommodating cavity (500) is formed among the supporting part (200), the upper polar plate (300) and the lower polar plate (400); a recess (600) opposite to the accommodating cavity (500) is arranged in an intermediate region of at least one of the upper polar plate (300) and the lower polar plate (400), and insulation is achieved between the upper polar plate (300) and a lower polar plate (400).

72. 发明授权

US09862595B2 Method for manufacturing thin-film support beam 有权
公开(公告)号：US09862595B2
公开(公告)日：2018-01-09
申请号：US15023057
申请日：2014-12-04
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Errong Jing
IPC分类号： H01L21/30 , H01L21/46 , B81C1/00
CPC分类号： B81C1/00142 , B81C2201/0108 , B81C2201/0109 , B81C2201/013
摘要： A method for manufacturing a film support beam includes: providing a substrate having opposed first and second surfaces; coating a sacrificial layer on the first surface of the substrate, and patterning the sacrificial layer; depositing a dielectric film on the sacrificial layer to form a dielectric film layer, and depositing a metal film on the dielectric film layer to form a metal film layer; patterning the metal film layer, and dividing a patterned area of the metal film layer into a metal film pattern of a support beam portion and a metal film pattern of a non-support beam portion, wherein a width of the metal film pattern of the support beam portion is greater than a width of a final support beam pattern, and a width of the metal film pattern of the non-support beam portion is equal to a width of a width of a final non-support beam pattern at the moment; photoetching and etching on the metal film layer and the dielectric film layer to obtain the final support beam pattern, the final non-support beam pattern and a final dielectric film layer, wherein the final dielectric film layer serves as a support film of the final support beam pattern and the final non-support beam pattern; and removing the sacrificial layer.

73. 发明授权

US09728472B2 Method for wafer etching in deep silicon trench etching process 有权
公开(公告)号：US09728472B2
公开(公告)日：2017-08-08
申请号：US14435955
申请日：2013-12-31
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Anna Zhang , Xiaoming Li
IPC分类号： H01L21/3065 , H01L21/66 , H01L21/683
CPC分类号： H01L22/26 , H01L21/3065 , H01L21/6831
摘要： A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S110); b. performing the sub-steps of a main process for the wafer, and the time for the sub-steps of the main process being shorter than the time required by the wafer main process; c. releasing the electrostatic adsorption of the electrostatic chuck on the wafer; d. determining whether the cumulative time of the sub-steps of the main process reaches a predetermined threshold or not, if so, performing the step e (S150), and if not, repeating the operations in the steps a to c (S140); and e. ending a wafer manufacturing process. The etching method avoids the wafer from continuous contact with the electrostatic chuck, reduces electrostatic accumulation on the surface of the wafer, and therefore solves the problem of resist reticulation on the surface of the wafer in the DSIE process.

74. 发明授权

US09595520B2 IGBT with built-in diode and manufacturing method therefor 有权
标题翻译：具有内置二极管的IGBT及其制造方法
公开(公告)号：US09595520B2
公开(公告)日：2017-03-14
申请号：US14901622
申请日：2014-06-09
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Xiaoshe Deng , Shuo Zhang , Qiang Rui , Genyi Wang
IPC分类号： H01L29/74 , H01L27/07 , H01L29/66 , H01L29/739 , H01L29/06 , H01L29/08 , H01L21/8249 , H01L29/868 , H01L29/40
CPC分类号： H01L27/0727 , H01L21/8249 , H01L29/0619 , H01L29/0684 , H01L29/0834 , H01L29/402 , H01L29/66333 , H01L29/7395 , H01L29/868
摘要： An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor substrate (1) of the first conduction type which has a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises an active region (100) and a terminal protection area (200) which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (1S1) of the active region (100), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers (10) of the first conduction type and second semiconductor layers (11) of the second conduction type of the active region, which are formed at the side of the second major surface (1S2) of the semiconductor substrate (1) alternately, wherein the IGBT only comprises the second semiconductor layers (11) in the terminal protection area (200) which is located at the side of the second major surface (1S2) of the semiconductor substrate (1).
摘要翻译：提供了具有内置二极管的绝缘栅双极转换器（IGBT）及其制造方法。 IGBT包括：具有第一主表面（1S1）和第二主表面（1S2）的第一导电类型的半导体衬底（1），其中半导体衬底（1）包括有源区（100）和端子保护区域（200），其位于有源区域的外侧; 绝缘栅晶体管单元，其形成在有源区（100）的第一主表面（1S1）侧，其中在其导通期间在其上形成第一导电类型的沟道; 以及形成在半导体衬底（1）的第二主表面（1S2）侧的第一导电类型和第二导电类型的有源区的第二半导体层（11）的第一半导体层（10）交替地，其中IGBT仅包括端子保护区域（200）中位于半导体衬底（1）的第二主表面（1S2）侧的第二半导体层（11）。

75. 发明授权

US09590029B2 Method for manufacturing insulated gate bipolar transistor 有权
标题翻译：绝缘栅双极晶体管的制造方法
公开(公告)号：US09590029B2
公开(公告)日：2017-03-07
申请号：US14902432
申请日：2014-08-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L29/06 , H01L29/66 , H01L29/739 , H01L29/10 , H01L29/40 , H01L29/16 , H01L29/20 , H01L29/161 , H01L29/04 , H01L21/761
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/401 , H01L29/407 , H01L29/408 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a polysilicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.
摘要翻译：一种用于制造绝缘栅双极晶体管（100）的方法，包括：提供衬底（10），在衬底（10）的前表面上形成场氧化物层（20），并形成端子保护环（23）; 通过使用有源区光掩模对有源区域氧化物层（20）进行光刻和蚀刻，通过使用光致抗蚀剂作为掩模膜将N型离子引入到衬底（10）中; 在所述场氧化物层（20）的蚀刻衬底（10）上沉积和形成多晶硅栅极（31），并在所述多晶硅栅极（31）上形成保护层; 在N型离子的导入区域上进行接合，然后形成载流子增强区域（41）。通过使用P阱光掩模进行光蚀刻，将P型离子引入载体增强区域（41）中，并执行连接推动然后形成P体区域; 通过多晶硅栅极进行N型离子的自对准引入到P体区域中，并进行结压并形成N型重掺杂区域; 在所述多晶硅栅极的两侧形成侧壁，将P型离子引入所述N型重掺杂区域中，并执行结推进，然后形成P型重掺杂区域; 并去除保护层，然后进行多晶硅栅极的引入和掺杂。该方法减少了设置载流子增强区域的正向压降。

76. 发明授权

US09553164B2 Method for manufacturing IGBT 有权
标题翻译：制造IGBT的方法
公开(公告)号：US09553164B2
公开(公告)日：2017-01-24
申请号：US14902205
申请日：2014-06-13
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Xuan Huang , Wanli Wang , Genyi Wang
IPC分类号： H01L21/00 , H01L29/66 , H01L29/10 , H01L21/304 , H01L21/306 , H01L29/08 , H01L29/49 , H01L23/31 , H01L29/739
CPC分类号： H01L29/66333 , H01L21/304 , H01L21/30604 , H01L21/30625 , H01L23/3171 , H01L29/0804 , H01L29/0834 , H01L29/1004 , H01L29/1095 , H01L29/4916 , H01L29/7395
摘要： A method for manufacturing an IGBT, comprising: providing a substrate having a first surface and a second surface and of a first or second type of electrical conductance; forming grooves at intervals on the first surface of the substrate; filling a semiconductor material of the second or first type of electrical conductance into the grooves to form channels, where the type of electrical conductance of the channels is different from the type of electrical conductance of the substrate; bonding on the first surface of the substrate to form a drift region of the second type of electrical conductance; forming a front-side structure of the IGBT on the basis of the drift region; thinning the substrate starting from the second surface of the substrate until the channels are exposed; and forming a rear-side metal electrode on the channels and the thinned substrate. The method has no specific requirement with respect to sheet flow capacity, nor requires a double-sided exposure machine apparatus, is compatible with a conventional process, and has a simple process and high efficiency.
摘要翻译：一种制造IGBT的方法，包括：提供具有第一表面和第二表面以及第一或第二类型电导的基板; 在基板的第一表面上间隔地形成槽; 将第二或第一类电导体的半导体材料填充到沟槽中以形成通道，其中通道的导电类型不同于衬底的电导的类型; 在所述衬底的所述第一表面上接合以形成所述第二类型电导的漂移区域; 基于漂移区域形成IGBT的前侧结构; 从衬底的第二表面开始稀释衬底，直到通道暴露; 以及在通道和薄化的基板上形成后侧金属电极。该方法对于纸张流动能力没有特别要求，也不需要双面曝光机装置，与常规方法兼容，并且具有简单的工艺和高效率。

77. 发明授权

US09543451B2 High voltage junction field effect transistor 有权
标题翻译：高压结场效应晶体管
公开(公告)号：US09543451B2
公开(公告)日：2017-01-10
申请号：US14407599
申请日：2013-06-10
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Guangtao Han
IPC分类号： H01L29/808 , H01L29/10 , H01L29/40 , H01L29/08 , H01L29/06
CPC分类号： H01L29/808 , H01L29/0653 , H01L29/0843 , H01L29/1058 , H01L29/1066 , H01L29/402
摘要： The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated.
摘要翻译：本发明公开了一种高电压JFET。高电压JFET包括位于第一导电型外延层上的第二导电类型漂移区; 位于所述第二导电型漂移区域中的第二导电型漏极重掺杂区域; 位于所述第二导电型漂移区和所述第二导电型漏极重掺杂区的一侧的漏极端氧区; 位于第二导电型漂移区侧的第一导电型阱区; 第二导电型源极重掺杂区域和位于第一导电类型阱区域上的第一导电类型栅极重掺杂区域和栅极源极氧区域; 位于所述第二导电型源极重掺杂区域和所述第二导电型漂移区域之间的第二导电型沟道层; 位于第二导电型沟道层上的电介质层和场电极板。其中漏极电极从第二导电类型漏极重掺杂区域引出; 源极电极从场电极板和第二导电类型源重掺杂区域的连接引出; 并且从第一导电型栅极重掺杂区域引出栅电极。晶体管具有高击穿电压，易于集成。

78. 发明申请

US20160379974A1 MANUFACTURING METHOD FOR REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR 有权
标题翻译：反向绝缘栅双极晶体管的制造方法
公开(公告)号：US20160379974A1
公开(公告)日：2016-12-29
申请号：US14902519
申请日：2014-08-19
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shuo ZHANG , Qiang RUI , Genyi WANG , Xiaoshe DENG
IPC分类号： H01L27/06 , H01L29/739 , H01L29/06 , H01L21/265 , H01L21/304 , H01L29/10 , H01L29/66 , H01L21/3065
CPC分类号： H01L27/0664 , H01L21/263 , H01L21/26513 , H01L21/304 , H01L21/3065 , H01L29/0638 , H01L29/0834 , H01L29/1095 , H01L29/66333 , H01L29/7395
摘要： A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.
摘要翻译：一种用于反向导通绝缘栅双极晶体管的制造方法，其制造方法的特征在于使用多晶硅来填充反向导通绝缘栅双极晶体管背面的沟槽。反向导通绝缘栅双极晶体管背面的反向导通二极管的参数可以简单地通过精确控制多晶硅的掺杂浓度来控制，从而对过程控制要求相对较低。反向导通绝缘栅双极晶体管制造方法对于工艺控制的要求相对较低，制造难度相对较小。

79. 发明申请

US20160372571A1 REVERSE CONDUCTION INSULATED GATE BIPOLAR TRANSISTOR (IGBT) MANUFACTURING METHOD 有权
标题翻译：反向绝缘栅双极晶体管（IGBT）制造方法
公开(公告)号：US20160372571A1
公开(公告)日：2016-12-22
申请号：US14902302
申请日：2014-09-02
申请人： CSMC TECHNOLOGIES FAB1 CO.,LTD.
发明人： Wanli Wang , Xiaoshe DENG , Genyi WANG , Qiang RUI
IPC分类号： H01L29/66 , H01L21/308 , H01L29/06 , H01L21/265 , H01L29/739 , H01L21/268
CPC分类号： H01L29/66333 , H01L21/26513 , H01L21/268 , H01L21/308 , H01L21/3247 , H01L29/0657 , H01L29/0696 , H01L29/0834 , H01L29/41716 , H01L29/7395
摘要： A reverse conducting insulated gate bipolar transistor (IGBT) manufacturing method, comprising the following steps: providing a substrate having an IGBT structure formed on the front surface thereof; implanting P+ ions onto the back surface of the substrate; forming a channel on the back surface of the substrate through photolithography and etching processes; planarizing the back surface of the substrate through a laser scanning process to form P-type and N-type interval structures; and forming a back surface collector by conducting a back metalizing process on the back surface of the substrate. Laser scanning process can process only the back surface structure requiring annealing, thus solve the problem of the front surface structure of the reverse conducting IGBT restricting back surface annealing to a low temperature, improving the P-type and N-type impurity activation efficiency in the back surface structure of the reverse conducting IGBT, and enhancing the performance of the reverse conducting IGBT.
摘要翻译：一种反向导通绝缘栅双极晶体管（IGBT）制造方法，包括以下步骤：提供在其前表面上形成有IGBT结构的基板; 将P +离子注入衬底的背面; 通过光刻和蚀刻工艺在衬底的背表面上形成通道; 通过激光扫描工艺平坦化衬底的背面以形成P型和N型间隔结构; 以及通过在所述基板的背面进行背面金属化处理而形成背面集电体。激光扫描过程只能处理需要退火的背面结构，从而解决了限制背面退火至低温的反向导通IGBT的前表面结构的问题，提高了P型和N型杂质的活化效率反向导通IGBT的背面结构，提高反向导通IGBT的性能。

80. 发明授权

US09502534B2 Preparation method for power diode 有权
标题翻译：功率二极管的制备方法
公开(公告)号：US09502534B2
公开(公告)日：2016-11-22
申请号：US14902294
申请日：2014-09-12
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Genyi Wang , Xiaoshe Deng , Dongfei Zhou
IPC分类号： H01L29/00 , H01L29/66 , H01L21/02 , H01L29/06 , H01L21/311 , H01L21/28 , H01L21/266 , H01L21/027 , H01L21/265 , H01L21/3213 , H01L21/324 , H01L21/768 , H01L29/167
CPC分类号： H01L29/66666 , H01L21/02576 , H01L21/0273 , H01L21/26513 , H01L21/266 , H01L21/28035 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/32139 , H01L21/324 , H01L21/768 , H01L29/0619 , H01L29/167 , H01L29/6609 , H01L29/66712 , H01L29/861
摘要： A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20) growing on the front surface of the substrate (10), and the N-type layer (20) having a first surface deviating from the substrate (10); forming a terminal protection ring (31, 32, 33); forming an oxide layer (50), and performing knot pushing on the terminal protection ring (31, 32, 33); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer (50) of the active region, and forming a gate oxide layer (60) on the first surface of the N-type layer (20) of the active region; depositing on the gate oxide layer (60) to form a polysilicon layer (70); conducting photoetching using a polysilicon photoetching plate, taking a photoresist (40) as a mask layer to inject P-type ions into the N-type layer (20), and forming a P-type body region (82) beneath the polysilicon layer (70) through ion scattering; forming an N-type heavily doped region; forming a P+region; conducting thermal annealing, activating injected impurities and removing the photoresist (40); and conducting metallization processing on the first surface and the back surface of the substrate (10).
摘要翻译：一种用于功率二极管的制备方法，包括：提供基板（10），所述基板（10）具有前表面和与所述前表面相对的后表面的N型层（20），所述N型层（20）在所述基板（10）和具有偏离所述基板（10）的第一表面的所述N型层（20）。形成端子保护环（31,32,33）; 形成氧化物层（50），并且对所述端子保护环（31,32,33）施加结压力; 使用有源区的光刻板进行光蚀刻，蚀刻有源区的氧化层（50），在有源区的N型层（20）的第一面上形成栅极氧化层（60）沉积在栅极氧化物层（60）上以形成多晶硅层（70）; 使用多晶硅光刻板进行光蚀刻，以光致抗蚀剂（40）作为掩模层将P型离子注入到N型层（20）中，并在多晶硅层下形成P型体区（82） 70）通过离子散射; 形成N型重掺杂区域; 形成P +区; 进行热退火，激活注入的杂质和去除光致抗蚀剂（40）; 以及在所述基板（10）的所述第一表面和所述背面上进行金属化处理。

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