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1. 发明授权

US10062746B2 Semiconductor rectifier and manufacturing method thereof 有权
公开(公告)号：US10062746B2
公开(公告)日：2018-08-28
申请号：US15539554
申请日：2015-09-10
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Xiaoshe Deng , Dongfei Zhou
IPC分类号： H01L29/06 , H01L21/78 , H01L21/02 , H01L21/04 , H01L29/861 , H02M3/158 , H01L21/768
摘要： A semiconductor rectifying device includes a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a filling structure, an upper electrode, a guard ring, and a guard layer. The epitaxial layer defines a plurality of trenches thereon. The filling structure includes an insulating material formed on the inner surface of the trench and a conductive material filled in the trench. A doped region of a second conductivity type is formed in the surface of the epitaxial layer between the filling structures. A method of manufacturing a semiconductor rectifying device includes forming an epitaxial layer of a first conductivity type on a substrate of the first conductivity type, defining a plurality of trenches on the epitaxial layer, forming a plurality of filling structures in the plurality of trenches, and forming a doped region in the epitaxial layer between the filling structures.

2. 发明授权

US09673193B2 Manufacturing method for reverse conducting insulated gate bipolar transistor 有权
公开(公告)号：US09673193B2
公开(公告)日：2017-06-06
申请号：US14902519
申请日：2014-08-19
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shuo Zhang , Qiang Rui , Genyi Wang , Xiaoshe Deng
IPC分类号： H01L27/06 , H01L29/66 , H01L29/739 , H01L21/3065 , H01L21/265 , H01L21/304 , H01L29/10 , H01L29/06
CPC分类号： H01L27/0664 , H01L21/263 , H01L21/26513 , H01L21/304 , H01L21/3065 , H01L29/0638 , H01L29/0834 , H01L29/1095 , H01L29/66333 , H01L29/7395
摘要： A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.

3. 发明授权

US09583587B2 Method for manufacturing injection-enhanced insulated-gate bipolar transistor 有权
标题翻译：制造注入增强绝缘栅双极晶体管的方法
公开(公告)号：US09583587B2
公开(公告)日：2017-02-28
申请号：US14902220
申请日：2014-07-23
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Wanli Wang , Xiaoshe Deng , Genyi Wang , Xuan Huang
IPC分类号： H01L21/33 , H01L21/22 , H01L21/38 , H01L29/66 , H01L29/739 , H01L29/10 , H01L29/06 , H01L21/265 , H01L21/266 , H01L21/225 , H01L21/324
CPC分类号： H01L29/66348 , H01L21/2253 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L29/063 , H01L29/1095 , H01L29/7397
摘要： A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a p-type doped layer (14) is formed on the n-type substrate (12); a hard layer (20) is formed on the p-type doped layer (14); a groove (40) extending to the n-type substrate (12) is formed by etching on the p-type doped layer (14); an n-type doped layer (50) is formed on the sidewalls and bottom of the groove (40); the hard layer (20) is removed; p-type impurities of the p-type doped layer (14) and n-type impurities of the n-type doped layer (50) are driven in together, where the p-type impurities are diffused to form a p-type base region (60), and the n-type impurities are diffused to form an n-type buffer layer (70); a gated oxide dielectric layer (80) is formed on the surface of the groove (40); and, a polysilicon layer (90) is deposited in the groove having formed therein the gate oxide dielectric layer (80). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer (14) and the n-type doped layer (50) are driven in together to form the p-type base region (60) and the n-type buffer layer (70), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.
摘要翻译：一种用于制造注射增强绝缘栅双极晶体管的方法，包括以下步骤：提供n型衬底（12）; 在n型衬底（12）上形成p型掺杂层（14）。在p型掺杂层（14）上形成硬质层（20）。通过蚀刻在p型掺杂层（14）上形成延伸到n型衬底（12）的沟槽（40）。在凹槽（40）的侧壁和底部上形成n型掺杂层（50）; 去除硬层（20）; p型掺杂层（14）的p型杂质和n型掺杂层（50）的n型杂质一起被驱动，其中p型杂质被扩散以形成p型基极区域（60），并且n型杂质扩散以形成n型缓冲层（70）; 在凹槽（40）的表面上形成栅极氧化物介电层（80）; 并且在其中形成有栅极氧化物介电层（80）的沟槽中沉积多晶硅层（90）。在注入增强型绝缘栅双极晶体管的制造方法中，p型掺杂层（14）和n型掺杂层（50）一起被驱动以形成p型基极区（60）和 n型缓冲层（70）仅需要一个驱动工艺，与用于制造注射增强型绝缘栅双极晶体管的传统方法相比，生产周期缩短。

4. 发明申请

US20160380048A1 METHOD FOR MANUFACTURING INSULATED GATE BIPOLAR TRANSISTOR 有权
标题翻译：制造绝缘栅双极晶体管的方法
公开(公告)号：US20160380048A1
公开(公告)日：2016-12-29
申请号：US14902432
申请日：2014-08-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L29/06 , H01L29/739 , H01L29/10 , H01L21/761 , H01L29/16 , H01L29/20 , H01L29/161 , H01L29/04 , H01L29/66 , H01L29/40
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/401 , H01L29/407 , H01L29/408 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a polysilicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.
摘要翻译：一种用于制造绝缘栅双极晶体管（100）的方法，包括：提供衬底（10），在衬底（10）的前表面上形成场氧化物层（20），并形成端子保护环（23）; 通过使用有源区光掩模对有源区域氧化物层（20）进行光刻和蚀刻，通过使用光致抗蚀剂作为掩模膜将N型离子引入到衬底（10）中; 在所述场氧化物层（20）的蚀刻衬底（10）上沉积和形成多晶硅栅极（31），并在所述多晶硅栅极（31）上形成保护层; 在N型离子的导入区域上进行接合，然后形成载流子增强区域（41）。通过使用P阱光掩模进行光蚀刻，将P型离子引入载体增强区域（41）中，并执行连接推动然后形成P体区域; 通过多晶硅栅极进行N型离子的自对准引入到P体区域中，并进行结压并形成N型重掺杂区域; 在所述多晶硅栅极的两侧形成侧壁，将P型离子引入所述N型重掺杂区域中，并执行结推进，然后形成P型重掺杂区域; 并去除保护层，然后进行多晶硅栅极的引入和掺杂。该方法减少了设置载流子增强区域的正向压降。

5. 发明授权

US10084036B2 Insulated gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US10084036B2
公开(公告)日：2018-09-25
申请号：US15840791
申请日：2017-12-13
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L21/338 , H01L21/336 , H01L29/06 , H01L29/16 , H01L21/761 , H01L29/04 , H01L29/161 , H01L29/20 , H01L29/10 , H01L29/739 , H01L29/66
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

6. 发明授权

US09881994B2 Insulated gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US09881994B2
公开(公告)日：2018-01-30
申请号：US14902284
申请日：2014-08-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L21/332 , H01L29/06 , H01L29/66 , H01L29/739 , H01L29/10 , H01L21/761 , H01L29/04 , H01L29/16 , H01L29/161 , H01L29/20
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

7. 发明授权

US09607851B2 Method for removing polysilicon protection layer on a back face of an IGBT having a field stop structure 有权
公开(公告)号：US09607851B2
公开(公告)日：2017-03-28
申请号：US14411978
申请日：2013-07-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Qiang Rui , Shuo Zhang , Genyi Wang , Xiaoshe Deng
IPC分类号： H01L21/311 , H01L21/3213 , H01L29/66 , H01L21/321
CPC分类号： H01L21/31116 , H01L21/32105 , H01L21/32137 , H01L29/66325 , H01L29/66333
摘要： Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.

8. 发明授权

US09443926B2 Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor 有权
标题翻译：场阻反向绝缘栅双极晶体管及其制造方法
公开(公告)号：US09443926B2
公开(公告)日：2016-09-13
申请号：US14901606
申请日：2014-06-06
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shuo Zhang , Qiang Rui , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L29/74 , H01L29/06 , H01L29/66 , H01L29/739 , H01L23/528 , H01L23/532 , H01L23/31
CPC分类号： H01L29/0607 , H01L23/3157 , H01L23/3171 , H01L23/528 , H01L23/53219 , H01L23/53247 , H01L29/0619 , H01L29/0834 , H01L29/66325 , H01L29/66333 , H01L29/7393 , H01L29/7395
摘要： A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).
摘要翻译：场阻反向导通绝缘栅双极晶体管及其制造方法。晶体管包括端子结构（200）和有源区（100）。场阻反向导通绝缘栅双极晶体管的底层是N型衬垫，衬垫的背面设置有N型电场停止层（1），电场停止层的一个表面在背衬P型结构（10）的背面设置有背面金属层（12）的背面P型结构（10）的表面。在有源区（100）中形成有从背面P型结构（10）贯穿电场停止层（1）的多个多晶硅填充结构（11）。

9. 发明申请

US20150155182A1 METHOD FOR REMOVING A POLYSILICON PROTECTION LAYER ON A BACK FACE OF AN IGBT HAVING A FIELD STOP STRUCTURE 有权
标题翻译：在具有现场停止结构的IGBT的背面上移除多晶硅保护层的方法
公开(公告)号：US20150155182A1
公开(公告)日：2015-06-04
申请号：US14411978
申请日：2013-07-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Qiang Rui , Shuo Zhang , Genyi Wang , Xiaoshe Deng
IPC分类号： H01L21/311 , H01L29/66
CPC分类号： H01L21/31116 , H01L21/32105 , H01L21/32137 , H01L29/66325 , H01L29/66333
摘要： Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.
摘要翻译：公开了一种在具有场停止结构（10）的IGBT的背面上去除多晶硅保护层（12）的方法。该方法包括在IGBT的背面上热氧化多晶硅保护层（12），直到在位于多晶硅保护层（12）上方的栅极氧化物层（11）上终止氧化以形成二氧化硅层（13），并通过干式蚀刻工艺除去形成的二氧化硅层（13）和栅极氧化物层（11）。去除保护层的方法更容易控制。

10. 发明授权

US09954074B2 Insulated gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US09954074B2
公开(公告)日：2018-04-24
申请号：US14902517
申请日：2014-07-22
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Xiaoshe Deng , Genyi Wang , Dongfei Zhou
IPC分类号： H01L29/66 , H01L29/40 , H01L29/739 , H01L29/06 , H01L29/10 , H01L21/02 , H01L21/265
CPC分类号： H01L29/66333 , H01L21/02233 , H01L21/26513 , H01L29/0619 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/7395
摘要： An insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises a semiconductor substrate (1) of a first conductive type, which is provided with a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises a primitive cell area (2) and a terminal protection area (4) which is located outside the primitive cell area; a first semiconductor layer (5) of a first conductive type which is formed at the side of the first major surface of the semiconductor substrate (1), wherein the doping concentration of the first semiconductor layer (5) is higher than the doping concentration of the semiconductor substrate (1); and an insulated gate transistor unit which is formed at the side of the first major surface of the first semiconductor layer (5) in the primitive cell area, wherein the insulated gate transistor unit is conducted, a channel of a first conductive type is formed. Compared with the prior art, the present invention not only can improve the voltage resistance reliability of the insulted gate bipolar transistor, but also can reduce the forward conductive voltage drop of the insulated gate bipolar transistor.

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