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1. 发明申请

US20160380048A1 METHOD FOR MANUFACTURING INSULATED GATE BIPOLAR TRANSISTOR 有权
标题翻译：制造绝缘栅双极晶体管的方法
公开(公告)号：US20160380048A1
公开(公告)日：2016-12-29
申请号：US14902432
申请日：2014-08-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L29/06 , H01L29/739 , H01L29/10 , H01L21/761 , H01L29/16 , H01L29/20 , H01L29/161 , H01L29/04 , H01L29/66 , H01L29/40
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/401 , H01L29/407 , H01L29/408 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a polysilicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.
摘要翻译：一种用于制造绝缘栅双极晶体管（100）的方法，包括：提供衬底（10），在衬底（10）的前表面上形成场氧化物层（20），并形成端子保护环（23）; 通过使用有源区光掩模对有源区域氧化物层（20）进行光刻和蚀刻，通过使用光致抗蚀剂作为掩模膜将N型离子引入到衬底（10）中; 在所述场氧化物层（20）的蚀刻衬底（10）上沉积和形成多晶硅栅极（31），并在所述多晶硅栅极（31）上形成保护层; 在N型离子的导入区域上进行接合，然后形成载流子增强区域（41）。通过使用P阱光掩模进行光蚀刻，将P型离子引入载体增强区域（41）中，并执行连接推动然后形成P体区域; 通过多晶硅栅极进行N型离子的自对准引入到P体区域中，并进行结压并形成N型重掺杂区域; 在所述多晶硅栅极的两侧形成侧壁，将P型离子引入所述N型重掺杂区域中，并执行结推进，然后形成P型重掺杂区域; 并去除保护层，然后进行多晶硅栅极的引入和掺杂。该方法减少了设置载流子增强区域的正向压降。

2. 发明授权

US10062746B2 Semiconductor rectifier and manufacturing method thereof 有权
公开(公告)号：US10062746B2
公开(公告)日：2018-08-28
申请号：US15539554
申请日：2015-09-10
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Xiaoshe Deng , Dongfei Zhou
IPC分类号： H01L29/06 , H01L21/78 , H01L21/02 , H01L21/04 , H01L29/861 , H02M3/158 , H01L21/768
摘要： A semiconductor rectifying device includes a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a filling structure, an upper electrode, a guard ring, and a guard layer. The epitaxial layer defines a plurality of trenches thereon. The filling structure includes an insulating material formed on the inner surface of the trench and a conductive material filled in the trench. A doped region of a second conductivity type is formed in the surface of the epitaxial layer between the filling structures. A method of manufacturing a semiconductor rectifying device includes forming an epitaxial layer of a first conductivity type on a substrate of the first conductivity type, defining a plurality of trenches on the epitaxial layer, forming a plurality of filling structures in the plurality of trenches, and forming a doped region in the epitaxial layer between the filling structures.

3. 发明授权

US09954074B2 Insulated gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US09954074B2
公开(公告)日：2018-04-24
申请号：US14902517
申请日：2014-07-22
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Xiaoshe Deng , Genyi Wang , Dongfei Zhou
IPC分类号： H01L29/66 , H01L29/40 , H01L29/739 , H01L29/06 , H01L29/10 , H01L21/02 , H01L21/265
CPC分类号： H01L29/66333 , H01L21/02233 , H01L21/26513 , H01L29/0619 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/7395
摘要： An insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises a semiconductor substrate (1) of a first conductive type, which is provided with a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises a primitive cell area (2) and a terminal protection area (4) which is located outside the primitive cell area; a first semiconductor layer (5) of a first conductive type which is formed at the side of the first major surface of the semiconductor substrate (1), wherein the doping concentration of the first semiconductor layer (5) is higher than the doping concentration of the semiconductor substrate (1); and an insulated gate transistor unit which is formed at the side of the first major surface of the first semiconductor layer (5) in the primitive cell area, wherein the insulated gate transistor unit is conducted, a channel of a first conductive type is formed. Compared with the prior art, the present invention not only can improve the voltage resistance reliability of the insulted gate bipolar transistor, but also can reduce the forward conductive voltage drop of the insulated gate bipolar transistor.

4. 发明申请

US20160307995A1 INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：绝缘栅双极晶体管及其制造方法
公开(公告)号：US20160307995A1
公开(公告)日：2016-10-20
申请号：US14902284
申请日：2014-08-25
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L29/06 , H01L29/10 , H01L29/16 , H01L29/66 , H01L29/20 , H01L29/04 , H01L21/761 , H01L29/739 , H01L29/161
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.
摘要翻译：提供绝缘栅双极晶体管（100）。绝缘栅双极型晶体管（100）的基板（10）为N型。 P型区域（16）设置在N型基板的背面。背面金属结构（18）设置在P型区域（16）的背面。端子保护环设置在端子结构中。在活性区域中的多晶硅栅极（31）设置在基板（10）的前表面上。侧壁（72）设置在基板（10）上的多晶硅栅极（31）的两侧。覆盖有多晶硅栅极（31）和侧壁（72）的层间介质（81）设置在基板（10）上。层间介质（81）被金属引线层（91）覆盖。在有源区域中的衬底（10）中设置有N型载流子增强区（41）。 P型体区域（51）设置在载体增强区域（41）中。 N型重掺杂区域（61）设置在P型体区域（51）中。 P型重掺杂区域（71）设置在N型重掺杂区域（61）中。在P型重掺杂区域（71）的表面上形成深度为0.15至0.3微米的向内凹入的浅凹坑（62）。通过设置载流子增强区域（41），可以增加沟道的载流子浓度并且可以减小正向压降; 此外，浅坑（62）可以使器件获得良好的杂质分布和大的金属接触面积，从而提高器件的性能。

5. 发明授权

US10084036B2 Insulated gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US10084036B2
公开(公告)日：2018-09-25
申请号：US15840791
申请日：2017-12-13
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L21/338 , H01L21/336 , H01L29/06 , H01L29/16 , H01L21/761 , H01L29/04 , H01L29/161 , H01L29/20 , H01L29/10 , H01L29/739 , H01L29/66
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

6. 发明授权

US09881994B2 Insulated gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US09881994B2
公开(公告)日：2018-01-30
申请号：US14902284
申请日：2014-08-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L21/332 , H01L29/06 , H01L29/66 , H01L29/739 , H01L29/10 , H01L21/761 , H01L29/04 , H01L29/16 , H01L29/161 , H01L29/20
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

7. 发明授权

US09590029B2 Method for manufacturing insulated gate bipolar transistor 有权
标题翻译：绝缘栅双极晶体管的制造方法
公开(公告)号：US09590029B2
公开(公告)日：2017-03-07
申请号：US14902432
申请日：2014-08-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L29/06 , H01L29/66 , H01L29/739 , H01L29/10 , H01L29/40 , H01L29/16 , H01L29/20 , H01L29/161 , H01L29/04 , H01L21/761
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/401 , H01L29/407 , H01L29/408 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a polysilicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.
摘要翻译：一种用于制造绝缘栅双极晶体管（100）的方法，包括：提供衬底（10），在衬底（10）的前表面上形成场氧化物层（20），并形成端子保护环（23）; 通过使用有源区光掩模对有源区域氧化物层（20）进行光刻和蚀刻，通过使用光致抗蚀剂作为掩模膜将N型离子引入到衬底（10）中; 在所述场氧化物层（20）的蚀刻衬底（10）上沉积和形成多晶硅栅极（31），并在所述多晶硅栅极（31）上形成保护层; 在N型离子的导入区域上进行接合，然后形成载流子增强区域（41）。通过使用P阱光掩模进行光蚀刻，将P型离子引入载体增强区域（41）中，并执行连接推动然后形成P体区域; 通过多晶硅栅极进行N型离子的自对准引入到P体区域中，并进行结压并形成N型重掺杂区域; 在所述多晶硅栅极的两侧形成侧壁，将P型离子引入所述N型重掺杂区域中，并执行结推进，然后形成P型重掺杂区域; 并去除保护层，然后进行多晶硅栅极的引入和掺杂。该方法减少了设置载流子增强区域的正向压降。

8. 发明授权

US09502534B2 Preparation method for power diode 有权
标题翻译：功率二极管的制备方法
公开(公告)号：US09502534B2
公开(公告)日：2016-11-22
申请号：US14902294
申请日：2014-09-12
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Genyi Wang , Xiaoshe Deng , Dongfei Zhou
IPC分类号： H01L29/00 , H01L29/66 , H01L21/02 , H01L29/06 , H01L21/311 , H01L21/28 , H01L21/266 , H01L21/027 , H01L21/265 , H01L21/3213 , H01L21/324 , H01L21/768 , H01L29/167
CPC分类号： H01L29/66666 , H01L21/02576 , H01L21/0273 , H01L21/26513 , H01L21/266 , H01L21/28035 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/32139 , H01L21/324 , H01L21/768 , H01L29/0619 , H01L29/167 , H01L29/6609 , H01L29/66712 , H01L29/861
摘要： A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20) growing on the front surface of the substrate (10), and the N-type layer (20) having a first surface deviating from the substrate (10); forming a terminal protection ring (31, 32, 33); forming an oxide layer (50), and performing knot pushing on the terminal protection ring (31, 32, 33); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer (50) of the active region, and forming a gate oxide layer (60) on the first surface of the N-type layer (20) of the active region; depositing on the gate oxide layer (60) to form a polysilicon layer (70); conducting photoetching using a polysilicon photoetching plate, taking a photoresist (40) as a mask layer to inject P-type ions into the N-type layer (20), and forming a P-type body region (82) beneath the polysilicon layer (70) through ion scattering; forming an N-type heavily doped region; forming a P+region; conducting thermal annealing, activating injected impurities and removing the photoresist (40); and conducting metallization processing on the first surface and the back surface of the substrate (10).
摘要翻译：一种用于功率二极管的制备方法，包括：提供基板（10），所述基板（10）具有前表面和与所述前表面相对的后表面的N型层（20），所述N型层（20）在所述基板（10）和具有偏离所述基板（10）的第一表面的所述N型层（20）。形成端子保护环（31,32,33）; 形成氧化物层（50），并且对所述端子保护环（31,32,33）施加结压力; 使用有源区的光刻板进行光蚀刻，蚀刻有源区的氧化层（50），在有源区的N型层（20）的第一面上形成栅极氧化层（60）沉积在栅极氧化物层（60）上以形成多晶硅层（70）; 使用多晶硅光刻板进行光蚀刻，以光致抗蚀剂（40）作为掩模层将P型离子注入到N型层（20）中，并在多晶硅层下形成P型体区（82） 70）通过离子散射; 形成N型重掺杂区域; 形成P +区; 进行热退火，激活注入的杂质和去除光致抗蚀剂（40）; 以及在所述基板（10）的所述第一表面和所述背面上进行金属化处理。

9. 发明授权

US09502497B2 Method for preparing power diode 有权
标题翻译：功率二极管的制作方法
公开(公告)号：US09502497B2
公开(公告)日：2016-11-22
申请号：US14902270
申请日：2014-10-22
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Genyi Wang , Xiaoshe Deng , Shengrong Zong , Dongfei Zhou
IPC分类号： H01L29/00 , H01L29/06 , H01L29/66 , H01L21/266 , H01L21/265 , H01L21/311 , H01L21/324 , H01L21/027 , H01L29/10 , H01L21/321 , H01L21/3213
CPC分类号： H01L29/0619 , H01L21/0273 , H01L21/26513 , H01L21/266 , H01L21/31116 , H01L21/32105 , H01L21/32137 , H01L21/324 , H01L29/1095 , H01L29/1608 , H01L29/20 , H01L29/2003 , H01L29/402 , H01L29/41766 , H01L29/6606 , H01L29/66136 , H01L29/66204 , H01L29/66325 , H01L29/66333 , H01L29/66719 , H01L29/66727 , H01L29/7811 , H01L29/8611
摘要： A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a terminal protecting ring; forming an oxide layer (30), knot-pushing to the terminal protecting ring; forming a gate oxide layer (60), depositing a poly-silicon layer (70) on the gate oxide layer (60); depositing a SiO2 layer (80) on the surface of the poly-silicon layer (70) and a oxide layer (50); forming a N type heavy doped region (92); forming a P+ region; removing a photoresist, implanting P type ions using the SiO2 layer (80) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (70), the gate oxide layer (60) being etched, and removing the SiO2 layer (80); and processing a front surface metallization and a back surface metallization treatment. According to the method for preparing the power diode, by adjusting the isotropy etching level of the SiO2 layer and the ion implanting dose and energy, the threshold voltage of a DMOS structure can be adjusted, and the adjustment of the forward voltage drop for the device can be achieved.
摘要翻译：一种制备功率二极管的方法，包括：提供衬底（10），在衬底（10）的前表面上生长N型层（20）; 形成端保护环; 形成氧化物层（30），向所述端子保护环打结; 形成栅极氧化物层（60），在所述栅极氧化物层（60）上沉积多晶硅层（70）。在所述多晶硅层（70）的表面和氧化物层（50）上沉积SiO 2层（80）; 形成N型重掺杂区域（92）; 形成P +区; 去除光致抗蚀剂，使用SiO 2层（80）作为掩模层注入P型离子，形成P型体区; 热退火; 在所述多晶硅层（70）的开口部形成侧壁结构，蚀刻所述栅极氧化物层（60），除去所述SiO 2层（80）。以及处理前表面金属化和背面金属化处理。根据制备功率二极管的方法，通过调整SiO2层的各向同性蚀刻水平和离子注入剂量和能量，可以调整DMOS结构的阈值电压，并调整器件的正向压降可以实现。

10. 发明申请

US20160308029A1 PREPARATION METHOD FOR POWER DIODE 有权
标题翻译：功率二极管的制备方法
公开(公告)号：US20160308029A1
公开(公告)日：2016-10-20
申请号：US14902294
申请日：2014-09-12
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： Shengrong Zhong , Genyi Wang , Xiaoshe Deng , Dongfei Zhou
IPC分类号： H01L29/66 , H01L29/06 , H01L21/311 , H01L21/28 , H01L29/167 , H01L21/027 , H01L21/265 , H01L21/3213 , H01L21/324 , H01L21/768 , H01L21/02 , H01L21/266
CPC分类号： H01L29/66666 , H01L21/02576 , H01L21/0273 , H01L21/26513 , H01L21/266 , H01L21/28035 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/32139 , H01L21/324 , H01L21/768 , H01L29/0619 , H01L29/167 , H01L29/6609 , H01L29/66712 , H01L29/861
摘要： A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20) growing on the front surface of the substrate (10), and the N-type layer (20) having a first surface deviating from the substrate (10); forming a terminal protection ring (31, 32, 33); forming an oxide layer (50), and performing knot pushing on the terminal protection ring (31, 32, 33); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer (50) of the active region, and forming a gate oxide layer (60) on the first surface of the N-type layer (20) of the active region; depositing on the gate oxide layer (60) to form a polysilicon layer (70); conducting photoetching using a polysilicon photoetching plate, taking a photoresist (40) as a mask layer to inject P-type ions into the N-type layer (20), and forming a P-type body region (82) beneath the polysilicon layer (70) through ion scattering; forming an N-type heavily doped region; forming a P+region; conducting thermal annealing, activating injected impurities and removing the photoresist (40); and conducting metallization processing on the first surface and the back surface of the substrate (10).
摘要翻译：一种用于功率二极管的制备方法，包括：提供基板（10），所述基板（10）具有前表面和与所述前表面相对的后表面的N型层（20），所述N型层（20）在所述基板（10）和具有偏离所述基板（10）的第一表面的所述N型层（20）。形成端子保护环（31,32,33）; 形成氧化物层（50），并且对所述端子保护环（31,32,33）施加结压力; 使用有源区的光刻板进行光蚀刻，蚀刻有源区的氧化层（50），在有源区的N型层（20）的第一面上形成栅极氧化层（60）沉积在栅极氧化物层（60）上以形成多晶硅层（70）; 使用多晶硅光刻板进行光蚀刻，以光致抗蚀剂（40）作为掩模层将P型离子注入到N型层（20）中，并在多晶硅层下形成P型体区（82） 70）通过离子散射; 形成N型重掺杂区域; 形成P +区; 进行热退火，激活注入的杂质和去除光致抗蚀剂（40）; 以及在所述基板（10）的所述第一表面和所述背面上进行金属化处理。

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