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71. 发明授权

US09076552B2 Device including a dual port static random access memory cell and method for the formation thereof 有权
标题翻译：包括双端口静态随机存取存储器单元的装置及其形成方法
公开(公告)号：US09076552B2
公开(公告)日：2015-07-07
申请号：US13936775
申请日：2013-07-08
申请人： GLOBALFOUNDRIES Inc.
发明人： Torsten Schaefer , Dirk Fimmel
IPC分类号： G11C11/00 , G11C11/412 , H01L27/11 , G11C8/16
CPC分类号： G11C11/412 , G11C8/16 , H01L27/11 , H01L27/1104
摘要： A device includes a substrate and a dual port static random access memory cell. The substrate includes an N-well region, a first P-well region and a second P-well region. The first and second P-well regions are arranged on opposite sides of the N-well region and spaced apart along a width direction. The static random access memory cell includes first and second pull-up transistors that are provided in the N-well region, a first pair of pull-down transistors and a first pair of access transistors provided in the first P-well region, and a second pair of pull-down transistors and a second pair of access transistors provided in the second P-well region. Each of the first pair and the second pair of pull-down transistors includes a first pull-down transistor and a second pull-down transistor. Active regions of the first pull-down transistor and the second pull-down transistor are spaced apart along the width direction.
摘要翻译：一种器件包括衬底和双端口静态随机存取存储器单元。衬底包括N阱区，第一P阱区和第二P阱区。第一和第二P阱区域布置在N阱区域的相对侧上并且沿着宽度方向间隔开。静态随机存取存储单元包括设置在N阱区中的第一和第二上拉晶体管，第一对下拉晶体管和设置在第一P阱区中的第一对存取晶体管，以及第二对下拉晶体管和设置在第二P阱区域中的第二对存取晶体管。第一对和第二对下拉晶体管中的每一个包括第一下拉晶体管和第二下拉晶体管。第一下拉晶体管和第二下拉晶体管的有源区沿宽度方向间隔开。

72. 发明授权

US08990607B2 Memory interface circuits including calibration for CAS latency compensation in a plurality of byte lanes 有权
标题翻译：存储器接口电路，包括用于多个字节通道中的CAS等待时间补偿的校准
公开(公告)号：US08990607B2
公开(公告)日：2015-03-24
申请号：US14081806
申请日：2013-11-15
申请人： Uniquify, Incorporated
发明人： Jung Lee , Mahesh Goplan
IPC分类号： G06F1/00 , G06F1/12 , G06F1/04 , H03K19/173 , H03K19/00 , G11C11/00 , G11C8/16 , G01R35/00 , G01R27/28 , G06F12/00 , G11C29/00 , G01R31/28 , G06F1/08 , G06F13/16 , G06F13/42 , G11C29/02 , G11C29/50 , G06F12/06 , G11C7/22 , G06F3/06 , G06F1/14
CPC分类号： G11C7/1072 , G06F1/04 , G06F1/08 , G06F1/12 , G06F1/14 , G06F3/0619 , G06F3/065 , G06F3/067 , G06F12/0646 , G06F13/1689 , G06F13/4243 , G11C7/04 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.
摘要翻译：描述用于读取操作的存储器接口电路。该电路包括一个或多个控制器电路，一个或多个读数据延迟电路，用于为字节通道提供CAS延迟补偿。在系统中，根据不时执行的动态校准过程，使用控制器电路来确定和设置用于提供CAS等待时间补偿的读数据延迟电路的控制设置。在系统中，确定和设置用于提供CAS等待时间补偿的读数据延迟电路的控制设置在多个字节通道中的每一个中独立地并行地执行。

73. 发明授权

US08976576B2 Static random access memory structures 有权
标题翻译：静态随机存取存储器结构
公开(公告)号：US08976576B2
公开(公告)日：2015-03-10
申请号：US14057294
申请日：2013-10-18
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Jinming Chen , Stella Huang
IPC分类号： G11C11/412 , G11C11/419 , G11C5/06 , G11C8/16 , G11C5/02 , G11C7/12
CPC分类号： G11C8/16 , G11C5/06 , G11C7/12 , G11C11/412 , G11C11/419
摘要： A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is complementary to the first storage node. The static random access memory structure also includes a reading region having a first reading transfer gate and a second reading transfer gate, and a reading word line electrically connecting with the gate of the first reading transfer gate and the gate of the second reading transfer gate. Further, the static random access memory structure includes a writing region independent of the reading region having a first writing transfer gate and a second writing transfer gate and a writing word line electrically connecting with the gate of the first writing transfer gate and the gate of the second transfer gate.
摘要翻译：提供了一种静态随机存取存储器结构。静态随机存取存储器结构包括具有第一存储节点和与第一存储节点互补的第二存储节点的存储区域。静态随机存取存储器结构还包括具有第一读取传输门和第二读取传输门的读取区，以及与第一读取传送门的栅极和第二读取传送门的栅极电连接的读取字线。此外，静态随机存取存储器结构包括独立于具有第一写入传输门和第二写入传输门的读取区域的写入区域以及与第一写入传输门的栅极和第一写入传输门的栅极电连接的写入字线第二传输门。

74. 发明授权

US08964456B2 Semiconductor memory with similar RAM and ROM cells 有权
标题翻译：具有类似RAM和ROM单元的半导体存储器
公开(公告)号：US08964456B2
公开(公告)日：2015-02-24
申请号：US13457129
申请日：2012-04-26
申请人： Dan C. R. Jensen
发明人： Dan C. R. Jensen
IPC分类号： G11C11/00 , G11C11/40 , G11C17/10 , G11C17/12 , G11C8/16 , G11C11/411 , G11C11/412
CPC分类号： G11C11/40 , G11C8/16 , G11C11/005 , G11C11/4116 , G11C11/412 , G11C17/10 , G11C17/12
摘要： A semiconductor memory includes an array of volatile memory cells, wherein one of the volatile memory cells has transistors connected in a first memory cell circuit, and at least one non-volatile memory cell having transistors connected in a second memory cell circuit, wherein the transistors in the first memory cell circuit are at least one more than the transistors in the second memory cell circuit.
摘要翻译：一种半导体存储器包括易失性存储器单元阵列，其中一个易失性存储单元具有连接在第一存储单元电路中的晶体管，以及至少一个具有连接在第二存储单元电路中的晶体管的非易失性存储单元，其中晶体管在第一存储单元电路中的第二存储单元电路中的晶体管比第二存储单元电路中的晶体管至少多一个。

75. 发明授权

US08908466B2 Multi-column addressing mode memory system including an integrated circuit memory device 有权
标题翻译：多列寻址模式存储器系统，包括集成电路存储器件
公开(公告)号：US08908466B2
公开(公告)日：2014-12-09
申请号：US13860825
申请日：2013-04-11
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G11C8/14 , G11C8/16 , G11C8/12 , G11C8/10
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

76. 发明授权

US08891317B2 Volatile memory with a decreased consumption 有权
标题翻译：挥发性记忆，消耗减少
公开(公告)号：US08891317B2
公开(公告)日：2014-11-18
申请号：US13758536
申请日：2013-02-04
申请人： STMicroelectronics SA
发明人： Anis Feki , Jean-Christophe Lafont , David Turgis
IPC分类号： G11C8/00 , G11C7/00 , G11C5/06 , G11C5/02 , G11C11/419 , G11C8/12 , G11C8/14 , G11C8/16 , G11C14/00 , G11C13/00
CPC分类号： G11C7/00 , G11C8/00 , G11C8/12 , G11C8/14 , G11C8/16 , G11C11/419 , G11C13/0069 , G11C14/0054
摘要： A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.
摘要翻译：包括适于执行数据写入和读取操作的易失性存储单元的易失性存储器。存储单元以行和列排列，并且进一步分布在用于每一行的单独存储单元组中。存储器包括被配置为执行写操作的第一存储单元选择电路和与第一电路不同的第二存储单元选择电路，被配置为执行读操作。第一电路能够为每一行选择来自一组存储器单元的存储器单元用于写入操作。第二电路能够为每行选择来自存储器单元组之一的存储单元用于读取操作。

77. 发明授权

US08891289B2 Ten-transistor dual-port SRAM with shared bit-line architecture 有权
标题翻译：具有共享位线架构的十个晶体管双端口SRAM
公开(公告)号：US08891289B2
公开(公告)日：2014-11-18
申请号：US13869624
申请日：2013-04-24
申请人： National Chiao Tung University
发明人： Wei Hwang , Dao-Ping Wang
IPC分类号： G11C8/16 , G11C11/412
CPC分类号： G11C11/412
摘要： A 10-transistor dual-port SRAM with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set. The second memory cell has a second storage unit, a third switch set, and a fourth switch set. The second switch set is coupled to a complement first A-port bit line and a complement first B-port bit line, and connected to the first storage unit. The third switch set is connected to a complement second A-port bit line, a complement second B-port bit line, and the second storage unit. Thus, the second memory cell can make use of the third switch set to share the complement first A-port bit line and the complement first B-port bit line with the first memory cell.
摘要翻译：具有共享位线架构的10晶体管双端口SRAM包括第一存储单元和第二存储单元。第一存储单元具有第一存储单元，第一开关组和第二开关组。第二存储单元具有第二存储单元，第三开关组和第四开关组。第二开关组耦合到补码第一A端口位线和补码第一B端口位线，并连接到第一存储单元。第三开关组连接到补码第二A端口位线，补码第二B端口位线和第二存储单元。因此，第二存储器单元可以利用第三开关组来与第一存储器单元共享补码第一A端口位线和补码第一B端口位线。

78. 发明授权

US08848480B1 Synchronous multiple port memory with asynchronous ports 有权
标题翻译：具有异步端口的同步多端口存储器
公开(公告)号：US08848480B1
公开(公告)日：2014-09-30
申请号：US13873988
申请日：2013-04-30
申请人： Perry H. Pelley
发明人： Perry H. Pelley
IPC分类号： G11C8/16 , G11C7/10 , G11C7/22
CPC分类号： G11C8/16 , G11C7/1072 , G11C7/1075 , G11C7/22
摘要： A method of operating a multiport memory, which has first and second sets of word lines and bit lines for accessing a memory array, uses a first port and a second port for accesses during a first phase of a master clock and a third port and a fourth port during a second phase of the master clock. Each port has its own port clock, which clocks their own row and column addresses, that is no faster than the master clock. Assuming there is demand for it, four accesses occur for each cycle of the master clock. This has the effect of being able to be sure that a given access is complete within two cycles of the port clocks and can be operated at the rate of one access per cycle of the port clock.
摘要翻译：操作具有用于访问存储器阵列的第一和第二组字线和位线的多端口存储器的方法在主时钟和第三端口的第一阶段期间使用第一端口和第二端口用于存取，第四端口在主时钟的第二阶段。每个端口都有自己的端口时钟，它们自己的行和列地址进行时钟，这不比主时钟快。假设有需求，主时钟的每个周期都会进行四次访问。这具有能够确保给定的访问在端口时钟的两个周期内完成并且可以以每个端口时钟周期的一次访问的速率来操作的效果。

79. 发明授权

US08830783B2 Improving read stability of a semiconductor memory 有权
标题翻译：提高半导体存储器的读稳定性
公开(公告)号：US08830783B2
公开(公告)日：2014-09-09
申请号：US12929138
申请日：2011-01-03
申请人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Vincent Phillipe Schuppe , Yew Keong Chong , Hsin-Yu Chen
发明人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Vincent Phillipe Schuppe , Yew Keong Chong , Hsin-Yu Chen
IPC分类号： G11C8/00 , G11C11/419 , G11C11/418 , G11C11/41 , G11C11/413 , G11C8/08 , G11C7/22 , G11C8/10 , G11C8/16 , G11C11/412
CPC分类号： G11C7/222 , G11C8/08 , G11C8/10 , G11C8/16 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/418 , G11C11/419
摘要： A semiconductor memory storage device is disclosed. The memory comprises a plurality of storage cells for storing data each storage cell comprising an access control device for providing the storage cell with access to or isolation from a data access port in response to an access control signal, access control circuitry for transmitting the access control signal along an access control line to control a plurality of the access control devices connected to the access control line. The access control circuitry responds to a data access request signal by increasing a voltage level supplied to the access control line to a first voltage level at a first average rate and then in response to receipt of a further signal increasing the voltage level supplied to the access control line to the predetermined higher voltage level, in such a way that a further average rate of increase of the voltage level from the first to the predetermined higher voltage level is lower than the first average rate of increase to the first level.
摘要翻译：公开了一种半导体存储器存储装置。存储器包括用于存储数据的多个存储单元，每个存储单元包括访问控制设备，用于响应于访问控制信号向存储单元提供对数据访问端口的访问或与数据访问端口的隔离，存取控制电路用于发送访问控制信号沿着访问控制线路控制连接到访问控制线路的多个访问控制设备。访问控制电路通过将提供给访问控制线的电压电平以第一平均速率增加到第一电压电平来响应于数据访问请求信号，然后响应于接收到增加提供给访问的电压电平的另外的信号控制线到预定的较高电压电平，使得从第一电压到预定的较高电压电平的电压电平的进一步的平均增加率低于第一平均增长率至第一电平。

80. 发明授权

US08797790B1 Memory elements with soft error upset immunity 有权
标题翻译：内存元件具有软错误的不安定性
公开(公告)号：US08797790B1
公开(公告)日：2014-08-05
申请号：US12568638
申请日：2009-09-28
申请人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
发明人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
IPC分类号： G11C11/00 , G11C11/412 , G11C8/16
CPC分类号： G11C11/412 , G11C5/005 , G11C5/06 , G11C8/16 , G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.
摘要翻译：提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。每个存储元件可以各自具有形成双稳态元件，一对地址晶体管和连接在两个逆变器之间的一对相对较弱的晶体管的四个逆变器状晶体管对，其形成公共输出节点，其抵抗快速变化它的状态。晶体管可以以形成双稳态存储器元件的图案连接，该双稳态存储器元件由于辐射打击而抵抗软错误不正常事件。可以使用地址晶体管对将数据加载到存储器元件中并从存储器元件读出。

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