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71. 发明申请

US20110186855A1 Enhancement-Mode GaN MOSFET with Low Leakage Current and Improved Reliability 有权
标题翻译：具有低漏电流的增强型GaN MOSFET和改进的可靠性
公开(公告)号：US20110186855A1
公开(公告)日：2011-08-04
申请号：US12697235
申请日：2010-01-30
申请人： Jamal Ramdani
发明人： Jamal Ramdani
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/66431 , H01L21/02458 , H01L21/0254 , H01L21/28264 , H01L29/1054 , H01L29/2003 , H01L29/205 , H01L29/513 , H01L29/518 , H01L29/66462 , H01L29/66522 , H01L29/7787
摘要： An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.
摘要翻译：通过在AlGaN（或InAlGaN）阻挡层上利用SiO 2 / Si 3 N 4栅极绝缘层，形成具有低漏电流和提高的可靠性的增强型GaN MOSFET。 SiO 2 / Si 3 N 4栅极绝缘层的Si 3 N 4部分显着地减少了在栅极绝缘层和阻挡层之间的接合处的界面态的形成，而SiO 2 / Si 3 N 4栅极绝缘层的SiO 2部分显着降低了漏电流。

72. 发明申请

US20110180850A1 Configuration and manufacturing method of low-resistance gate structures for semiconductor devices and circuits 有权
标题翻译：半导体器件和电路的低电阻栅极结构的配置和制造方法
公开(公告)号：US20110180850A1
公开(公告)日：2011-07-28
申请号：US12657602
申请日：2010-01-25
申请人： Ishiang Shih , Chunong Qiu , Cindy X. Qui , Yi-Chi Shih
发明人： Ishiang Shih , Chunong Qiu , Cindy X. Qui , Yi-Chi Shih
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L21/0331 , H01L29/42316
摘要： The present invention provides methods for fabricating devices with low resistance structures involving a lift-off process. A radiation blocking layer is introduced between two resist layers in order to prevent intermixing of the photoresists. Cavities suitable for the formation of low resistance T-gates or L-gates can be obtained by a first exposure, developing, selective etching of blocking layer and a second exposure and developing. In another embodiment, a low resistance gate structure with pillars to enhance mechanical stability or strength is provided.
摘要翻译：本发明提供了用于制造涉及剥离过程的具有低电阻结构的器件的方法。在两个抗蚀剂层之间引入辐射阻挡层，以防止光致抗蚀剂的混合。可以通过第一次曝光，显影，选择性蚀刻阻挡层和第二曝光和显影来获得适于形成低电阻T形栅极或L-栅极的腔体。在另一个实施例中，提供了具有柱以提高机械稳定性或强度的低电阻门结构。

73. 发明申请

US20110147708A1 INCREASING CARRIER INJECTION VELOCITY FOR INTEGRATED CIRCUIT DEVICES 有权
标题翻译：增加集成电路设备的载波速度
公开(公告)号：US20110147708A1
公开(公告)日：2011-06-23
申请号：US12643848
申请日：2009-12-21
申请人： Marko Radosavljevic , Benjamin Chu-Kung , Gilbert Dewey , Niloy Mukherjee
发明人： Marko Radosavljevic , Benjamin Chu-Kung , Gilbert Dewey , Niloy Mukherjee
IPC分类号： H01L29/66 , H01L29/778 , H01L21/335
CPC分类号： H01L29/7783 , B82Y10/00 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7785 , H01L29/7848 , H01L29/802 , H01L29/803
摘要： Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。可以描述和/或要求保护其他实施例。

74. 发明授权

US07964897B2 Direct contact to area efficient body tie process flow 失效
标题翻译：直接接触区域有效的身体扎扎过程流程
公开(公告)号：US07964897B2
公开(公告)日：2011-06-21
申请号：US12177332
申请日：2008-07-22
申请人： Paul S. Fechner , Bradley Larsen , Gregor Dougal , Keith Golke
发明人： Paul S. Fechner , Bradley Larsen , Gregor Dougal , Keith Golke
IPC分类号： H01L29/76 , H01L21/335
CPC分类号： H01L21/84 , H01L29/66772 , H01L29/78615
摘要： A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout.
摘要翻译：提供了一种用于制造具有直接身体接头的浅沟槽隔离（STI）装置的工艺流程。工艺流程遵循类似于标准STI制造方法的步骤，除了在其中一个蚀刻步骤中，通过氮化物层和STI氧化物层直接将身体接头触点蚀刻到身体接合处。该过程流程提供了直接的身体接触以减轻浮体效应，但也消除了非直接身体接头接触配置中常见的滞后和瞬态扰动效应，而不需要布局的关键对准要求和关键尺寸控制。

75. 发明授权

US07947537B2 Metal oxide semiconductor, semiconductor element, thin film transistor and method of manufacturing thereof 有权
标题翻译：金属氧化物半导体，半导体元件，薄膜晶体管及其制造方法
公开(公告)号：US07947537B2
公开(公告)日：2011-05-24
申请号：US12341387
申请日：2008-12-22
申请人： Makoto Honda , Katsura Hirai
发明人： Makoto Honda , Katsura Hirai
IPC分类号： H01L21/335 , H01L29/10
CPC分类号： H01L29/7869
摘要： A method of manufacturing a metal oxide semiconductor comprising the step of: conducting a transformation treatment on a semiconductor precursor layer containing a metal salt to form the metal oxide semiconductor, wherein the metal salt comprises one or more metal salts selected from the group consisting of a nitrate, a sulfate, a phosphate, a carbonate, an acetate and an oxalate of a metal; and the semiconductor precursor layer is formed by coating a solution of the metal salt.
摘要翻译：一种制造金属氧化物半导体的方法，包括以下步骤：对含有金属盐的半导体前体层进行转变处理以形成金属氧化物半导体，其中所述金属盐包含一种或多种选自以下的金属盐：硝酸盐，硫酸盐，磷酸盐，碳酸盐，乙酸盐和草酸盐; 并且通过涂覆金属盐的溶液形成半导体前体层。

76. 发明申请

US20110062448A1 Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices 有权
标题翻译：场效应半导体器件及制造场效半导体器件的方法
公开(公告)号：US20110062448A1
公开(公告)日：2011-03-17
申请号：US12923266
申请日：2010-09-13
申请人： Ki-ha Hong , Jong-seob Kim , Jae-joon Oh , Jai-kwang Shin , Hyuk-soon Choi , In-jun Hwang , Ho-jung Kim
发明人： Ki-ha Hong , Jong-seob Kim , Jae-joon Oh , Jai-kwang Shin , Hyuk-soon Choi , In-jun Hwang , Ho-jung Kim
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/42316 , H01L29/7787
摘要： Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer.
摘要翻译：提供了场效应半导体器件及其制造方法，场效应半导体器件包括在第一半导体层的第一表面上的第二半导体层，以及分别在第二半导体层的两侧上的第一和第二第三半导体层，分别在第一和第二第三半导体层上的源极和漏极，以及在第一半导体层的第二表面上的栅电极。

77. 发明授权

US07883933B2 Method of making to small devices having self-assembled organic layers 有权
标题翻译：制造具有自组装有机层的小型器件的方法
公开(公告)号：US07883933B2
公开(公告)日：2011-02-08
申请号：US12586029
申请日：2009-09-16
申请人： Nikolai Borisovich Zhitenev
发明人： Nikolai Borisovich Zhitenev
IPC分类号： H01L51/40 , H01L21/335 , H01L21/8232
CPC分类号： H01L51/105 , H01L51/0068 , H01L51/441 , Y02E10/549 , Y02P70/521
摘要： In one embodiment of the invention, a method of fabricating a SAM device comprises the steps of: (a) providing a substrate having a top surface and a first metal electrode disposed on the top surface, (b) annealing the first metal electrode, (c) forming a SAM layer on a major surface of the first electrode, the SAM layer having a free surface such that the SAM is disposed between the free surface and the major surface of the first electrode, and (d) forming a second metal electrode on the free surface of the molecular layer. Forming step (d) includes the step of (d1) depositing the second metal electrode in at least two distinct depositions separated by an interruption period of time when essentially no deposition of the second metal takes place. SAM FETs fabricated using this method are also described.
摘要翻译：在本发明的一个实施例中，制造SAM器件的方法包括以下步骤：（a）提供具有顶表面和设置在顶表面上的第一金属电极的衬底，（b）退火第一金属电极， c）在所述第一电极的主表面上形成SAM层，所述SAM层具有自由表面，使得所述SAM设置在所述自由表面和所述第一电极的主表面之间，以及（d）形成第二金属电极在分子层的自由表面上。形成步骤（d）包括以下步骤：（d1）在基本上不发生第二金属的沉积的中断时间间隔的至少两个不同的沉积中沉积第二金属电极。还描述了使用该方法制造的SAM FET。

78. 发明申请

US20110024799A1 COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：化合物半导体器件及其制造方法
公开(公告)号：US20110024799A1
公开(公告)日：2011-02-03
申请号：US12845292
申请日：2010-07-28
申请人： Yuichi Minoura , Toshihide Kikkawa
发明人： Yuichi Minoura , Toshihide Kikkawa
IPC分类号： H01L29/205 , H01L21/20 , H01L21/335 , H01L33/00
CPC分类号： H01L21/30617 , B82Y20/00 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/02664 , H01L21/0331 , H01L29/0696 , H01L29/2003 , H01L29/402 , H01L29/41758 , H01L29/66462 , H01L29/7787 , H01L29/7788 , H01S5/0201 , H01S5/0216 , H01S5/0217 , H01S5/02476 , H01S5/34333
摘要： A method for manufacturing a compound semiconductor device includes forming a first compound semiconductor layer over a first substrate, the first compound semiconductor layer containing AlxGa1-xN (0≦x
摘要翻译：一种化合物半导体器件的制造方法，包括在第一衬底上形成第一化合物半导体层，所述第一化合物半导体层含有具有第一带隙的Al x Ga 1-x N（0＆lt; n 1; x 1）在所述第一化合物半导体层上形成第二化合物半导体层，所述第二化合物半导体层包含具有大于所述第一带隙的第二带隙的Al y In z Ga 1-y-z N（0

79. 发明申请

US20110018002A1 TRANSISTORS AND RECTIFIERS UTILIZING HYBRID ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：使用混合电极的晶体管和整流器及其制造方法
公开(公告)号：US20110018002A1
公开(公告)日：2011-01-27
申请号：US12843313
申请日：2010-07-26
申请人： Jing Chen , Chunhua Zhou
发明人： Jing Chen , Chunhua Zhou
IPC分类号： H01L29/778 , H01L21/335 , H01L29/205
CPC分类号： H01L29/7786 , H01L21/28575 , H01L29/1029 , H01L29/2003 , H01L29/205 , H01L29/41725 , H01L29/42312 , H01L29/66212 , H01L29/66462 , H01L29/872
摘要： Systems, methods, and apparatus described herein are associated with devices including hybrid electrodes. A heterostructure semiconductor transistor can include a III-N-type semiconductor heterostructure including a barrier layer overlying an active layer and a hybrid electrode region including a hybrid drain electrode region. Further, a heterostructure semiconductor rectifier can include a III-N-type semiconductor heterostructure and a hybrid electrode region including a hybrid cathode electrode region. Furthermore, the hybrid electrode region of the transistor and rectifier can include permanently trapped charge located under a Schottky contact of the hybrid electrode region.
摘要翻译：本文描述的系统，方法和装置与包括混合电极的装置相关联。异质结构半导体晶体管可以包括包括有源层上的阻挡层的III-N型半导体异质结构和包括混合漏电极区的混合电极区。此外，异质结构半导体整流器可以包括III-N型半导体异质结构和包括混合阴极电极区的混合电极区。此外，晶体管和整流器的混合电极区域可以包括位于混合电极区域的肖特基接触下的永久俘获的电荷。

80. 发明申请

US20100297821A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100297821A1
公开(公告)日：2010-11-25
申请号：US12852805
申请日：2010-08-09
申请人： Young Suk KIM
发明人： Young Suk KIM
IPC分类号： H01L21/335 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating a semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. The method includes forming an isolation region in a semiconductor substrate; forming a gate electrode over an element region defined by the isolation region formed in the semiconductor substrate; and forming a semiconductor lager in the element region at both sides of the gate electrode apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed.
摘要翻译：一种制造应用技术的半导体器件的制造方法，其中可以抑制由硅化引起的漏电流。该方法包括在半导体衬底中形成隔离区; 在由形成在半导体衬底中的隔离区限定的元件区域上形成栅电极; 以及在所述隔离区域的至少一部分的所述栅电极的两侧的所述元件区域中形成半导体层。通过这样做，即使形成硅化物层，也抑制了隔离区附近的尖峰的形成。因此，可以抑制由这种尖峰引起的漏电流。

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