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71. 发明授权

US08399321B2 Method for manufacturing memory device 有权
标题翻译：制造存储器件的方法
公开(公告)号：US08399321B2
公开(公告)日：2013-03-19
申请号：US13111745
申请日：2011-05-19
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/425
CPC分类号： H01L27/10867 , H01L21/26586 , H01L27/10873 , H01L29/1083 , H01L29/66659
摘要： The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor.
摘要翻译：提供了一种用于制造存储器件的方法。该方法包括：将第一杂质注入到与栅极导体结构相邻的衬底中，以在栅极导体结构的第一侧上形成源极区，在栅极导体结构的第二侧上形成漏极区; 将第二杂质注入到所述衬底中以形成邻近所述源极区设置的卤素注入区，其中所述晕圈注入区具有不降解所述存储器件的数据保留时间的掺杂浓度; 对所述漏极区进行退火处理，在所述漏极区域下方形成扩散区域，其中，控制所述退火处理的工艺温度，以确保所述扩散区域的掺杂浓度基本上等于保持电连接的阈值浓度在漏极和深沟槽电容器之间。

72. 发明授权

US08368132B2 Ferroelectric memory and manufacturing method thereof 有权
标题翻译：铁电存储器及其制造方法
公开(公告)号：US08368132B2
公开(公告)日：2013-02-05
申请号：US12873720
申请日：2010-09-01
申请人： Kouichi Nagai
发明人： Kouichi Nagai
IPC分类号： H01L29/76 , H01L21/00 , H01L21/8242
CPC分类号： H01L27/11509 , H01L28/55 , H01L28/65 , H01L28/75
摘要： Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.
摘要翻译：提供了一种铁电存储器，其包括硅衬底，形成在硅衬底上的晶体管和形成在晶体管上方的铁电电容器。铁电电容器包括下电极，形成在下电极上的铁电膜，形成在强电介质膜上的上电极和形成在上电极上的金属膜。

73. 发明授权

US08357600B2 Method for fabricating buried gate using pre landing plugs 有权
标题翻译：使用预先着陆插头制造埋栅的方法
公开(公告)号：US08357600B2
公开(公告)日：2013-01-22
申请号：US12613708
申请日：2009-11-06
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8242
CPC分类号： H01L21/28017 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/4236
摘要： A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.
摘要翻译：提供一种制造半导体器件的方法，该方法包括在衬底的整个表面上形成插头导电层，蚀刻插头导电层以形成着陆塞，蚀刻层压塞之间的衬底以形成沟槽，形成栅极绝缘层，并且形成在门绝缘层上部分地填充沟槽的掩埋栅极。

74. 发明申请

US20130011989A1 METHODS OF MANUFACTURING A DRAM DEVICE 失效
标题翻译：制造DRAM器件的方法
公开(公告)号：US20130011989A1
公开(公告)日：2013-01-10
申请号：US13540996
申请日：2012-07-03
申请人： Jong-Chul Park , Sang-Sup Jeong
发明人： Jong-Chul Park , Sang-Sup Jeong
IPC分类号： H01L21/8242
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10855 , H01L27/10876
摘要： In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.
摘要翻译：在制造DRAM器件的方法中，在衬底中形成掩埋型栅极。掩埋型栅极上形成封盖绝缘层图案。形成填充封盖绝缘层图案的部分之间的间隙的导电层图案，以及覆盖导电层图案和封盖绝缘层图案的绝缘夹层。蚀刻绝缘中间层，导电层图案，封盖绝缘层图案和基板的上部以形成开口，以及与第一焊盘区域接触的第一焊盘电极。间隔件形成在对应于第二垫区域的开口的侧壁上。第二焊盘电极形成在开口中。形成与第二焊盘电极电连接的位线和与第一焊盘电极电连接的电容器。

75. 发明授权

US08349683B2 Production method of a capacitor 有权
标题翻译：电容器的制作方法
公开(公告)号：US08349683B2
公开(公告)日：2013-01-08
申请号：US10573495
申请日：2004-09-24
申请人： Kazumi Naito
发明人： Kazumi Naito
IPC分类号： H01L21/8242 , H01L29/08 , H01L35/24 , H01L51/00
CPC分类号： H01G9/15 , H01G9/0032 , H01G9/0036 , H01G9/042 , H01G9/07 , H01G11/48 , H01G11/56 , Y02E60/13 , Y10T29/417
摘要： The present invention relates to a method for producing a capacitor comprising, as one electrode, an electric conductor having formed on the surface thereof a dielectric layer and, as the other electrode, a semiconductor layer formed on the electric conductor by energization using the electric conductor as the anode, wherein fine protrusions are formed on the dielectric layer before energization; a capacitor produced by the method thereof having a good capacitance appearance factor and a low ESR; and an electronic circuit and an electronic device using the capacitor.
摘要翻译：电容器的制造方法技术领域本发明涉及一种电容器的制造方法，其特征在于，具有作为一个电极的表面上形成有电介质层的电导体，作为另一个电极，通过使用所述导电体通电而形成在所述导电体上的半导体层作为阳极，其中在通电之前在电介质层上形成微细突起; 通过其具有良好的电容外观因子和低ESR的方法产生的电容器; 以及使用该电容器的电子电路和电子装置。

76. 发明授权

US08343830B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08343830B2
公开(公告)日：2013-01-01
申请号：US12059754
申请日：2008-03-31
申请人： Hideaki Kikuchi , Kouichi Nagai
发明人： Hideaki Kikuchi , Kouichi Nagai
IPC分类号： H01L21/8242
CPC分类号： H01L28/40 , H01L21/76814 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L2924/3011
摘要： There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective insulating film covering the metal wiring and the second insulating film, forming an insulating sidewall on a side of the metal wiring, forming a third insulating film on the insulating sidewall, forming a hole by etching the third insulating film under a condition that an etching rate of the insulating sidewall would be lower than that of the third insulating film, and forming a conductive plug inside the hole.
摘要翻译：提供了一种制造半导体器件的方法，包括在半导体衬底上形成第一绝缘膜，在第一绝缘膜上形成电容器，形成覆盖电容器的第二绝缘膜，在第二绝缘膜上形成金属布线形成覆盖所述金属布线和所述第二绝缘膜的第一电容器保护绝缘膜，在所述金属布线的侧面上形成绝缘侧壁，在所述绝缘侧壁上形成第三绝缘膜，通过蚀刻所述第三绝缘膜而形成孔绝缘侧壁的蚀刻速度比第三绝缘膜低的条件，在孔内形成导电塞。

77. 发明授权

US08324048B2 Metal capacitor and method of making the same including dielectric layer of different mechanical strength and dielectric constant regions 有权
标题翻译：金属电容器及其制造方法包括不同机械强度和介电常数区域的介电层
公开(公告)号：US08324048B2
公开(公告)日：2012-12-04
申请号：US13342109
申请日：2012-01-01
申请人： Chin-Sheng Yang
发明人： Chin-Sheng Yang
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/4763
CPC分类号： H01L23/5223 , H01L21/3105 , H01L21/312 , H01L21/3122 , H01L21/3124 , H01L21/31612 , H01L21/31629 , H01L21/31695 , H01L21/76825 , H01L21/76826 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A method of making a metal capacitor includes the following steps. A dielectric layer having a dual damascene metal interconnection and a damascene capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the damascene capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the dual damascene metal interconnection and the dielectric layer can be prevented.
摘要翻译：制造金属电容器的方法包括以下步骤。提供具有双镶嵌金属互连和大马士革电容电极的电介质层。然后，进行处理以增加围绕大马士革电容器电极的电介质层的介电常数。治疗可以是紫外线辐射，等离子体处理或离子注入。因此，金属电容器将具有更高的电容，并且可以防止双镶嵌金属互连和电介质层之间的RC延迟。

78. 发明申请

US20120302020A1 SOI Trench Dram Structure With Backside Strap 审中-公开
公开(公告)号：US20120302020A1
公开(公告)日：2012-11-29
申请号：US13568580
申请日：2012-08-07
申请人： Bruce B. DORIS , Kangguo CHENG , Ali KHAKIFIROOZ , Pranita KULKARNI , Ghavam G. SHAHIDI
发明人： Bruce B. DORIS , Kangguo CHENG , Ali KHAKIFIROOZ , Pranita KULKARNI , Ghavam G. SHAHIDI
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.

79. 发明申请

US20120261733A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120261733A1
公开(公告)日：2012-10-18
申请号：US13417806
申请日：2012-03-12
申请人： Kiyonori OYU
发明人： Kiyonori OYU
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10876 , H01L21/761 , H01L21/823481 , H01L27/10885 , H01L27/10894 , H01L29/1087 , H01L29/4941 , H01L29/78
摘要： A semiconductor device comprises a trench isolation. The trench isolation is formed in a surface of a semiconductor substrate to define an active region a well region, and a bottom of the trench isolation is positioned within the well region. The trench isolation includes a conductive wiring electrically connected to the well region and an insulating film which buries the conductive wiring in the bottom of the trench isolation. Semiconductor elements are disposed in the active region.
摘要翻译：半导体器件包括沟槽隔离。在半导体衬底的表面中形成沟槽隔离以限定有源区域的阱区域，并且沟槽隔离的底部位于阱区域内。沟槽隔离包括电连接到阱区的导电布线和将沟槽隔离的底部中的导电布线埋入的绝缘膜。半导体元件设置在有源区域中。

80. 发明申请

US20120231592A1 Methods Of Fabricating A Memory Device 有权
标题翻译：制造存储器件的方法
公开(公告)号：US20120231592A1
公开(公告)日：2012-09-13
申请号：US13469513
申请日：2012-05-11
申请人： Gordon Haller , Sanh Dang Tang , Steve Cummings
发明人： Gordon Haller , Sanh Dang Tang , Steve Cummings
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L21/823487 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10888
摘要： A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
摘要翻译：包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。

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