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71. 发明授权

US09705516B1 Reconfigurable phase-locked loop with optional LC oscillator capability 有权
公开(公告)号：US09705516B1
公开(公告)日：2017-07-11
申请号：US15224296
申请日：2016-07-29
申请人： Movellus Circuits, Inc.
发明人： Jeffrey Alan Fredenburg , Muhammad Faisal , David Michael Moore
IPC分类号： H03L7/06 , H03L7/099 , H03L7/081 , H03B5/12
CPC分类号： H03L7/0995 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03L7/0998
摘要： A reconfigurable phase-locked loop integrated circuit is disclosed which is coupleable to an inductor, and may include: a memory storing a plurality of configuration parameters; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller to generate a first control signals to the reconfigurable frequency and delay generator to generate the second output signal having the second output frequency when the reconfigurable frequency and delay generator is configured as the ring oscillator; and to generate a second plurality of control signals to the plurality of capacitive tuning circuits to generate the first output signal having the first output frequency when the reconfigurable frequency and delay generator is configured as the delay line circuit.

72. 发明授权

US09705512B1 Self-calibrating fractional-N phase lock loop and method thereof 有权
$Self-calibrating fractional-N phase lock loop and method thereof$
公开(公告)号：US09705512B1
公开(公告)日：2017-07-11
申请号：US15271182
申请日：2016-09-20
申请人： Realtek Semiconductor Corporation
发明人： Chi-Kung Kuan , Yu Zhao , Chia-Liang Lin
IPC分类号： H03L7/06 , H03L7/089 , H03L7/099 , H03L7/197
CPC分类号： H03L7/0891 , H03L7/0898 , H03L7/093 , H03L7/0995 , H03L7/1974 , H03L7/1976
摘要： A circuit receives a reference clock and output an output clock in accordance with a clock multiplication factor, the circuit comprising: a digitally controlled timing adjustment circuit, a timing detection circuit, a loop filter, a controllable oscillator, a clock divider, a modulator, and a calibration circuit, wherein the modulator is configured to modulate a clock multiplication factor into a division factor and also calculate a pre-known noise caused by the modulation, and the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop such that a frequency of the output clock is equal to a frequency of the reference clock multiplied by the clock multiplication, but a pre-known noise caused by the modulation is corrected by the digitally controlled timing adjustment circuit, which is calibrated by the calibration circuit in a closed-loop manner to minimize a correlation between the pre-known noise and an output of the timing detection circuit.

73. 发明授权

US09660657B2 Spread spectrum clock generator 有权
公开(公告)号：US09660657B2
公开(公告)日：2017-05-23
申请号：US14804704
申请日：2015-07-21
申请人： Renesas Electronics Corporation
发明人： Fumiyuki Adachi
IPC分类号： H03L7/06 , H03L7/189 , H04B1/707 , H03L7/197 , H03M7/30
CPC分类号： H03L7/189 , H03L7/0891 , H03L7/093 , H03L7/1976 , H03M7/3026 , H04B1/707
摘要： A spread spectrum clock generator includes: a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase difference between the reference clock signal and the feedback clock signal; a voltage-controlled oscillator that oscillates at an oscillating frequency corresponding to the control voltage, and generates an output clock signal; a delta-sigma modulator that receives a waveform signal for controlling spreading of a spectrum of the output clock signal, and outputs bits larger than 1 bit based on the waveform signal; a control circuit that controls a multiplication number according to an output signal of the delta-signal modulator; and a divider that generates the feedback clock signal by dividing the output clock signal according to the multiplication number controlled by the control circuit, and supplies the feedback clock signal to the phase comparing unit.

74. 发明授权

US09654093B2 Electronic device having a delay locked loop, and memory device having the same 有权
公开(公告)号：US09654093B2
公开(公告)日：2017-05-16
申请号：US14955051
申请日：2015-12-01
申请人： Samsung Electronics Co., Ltd.
发明人： Won-Joo Yun , Yong Shim
IPC分类号： H03L7/06 , H03K7/08 , H03L7/085 , H03K5/156
CPC分类号： H03K7/08 , H03K5/1565 , H03L7/085
摘要： An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal. The delay control circuit is configured to generate the delay control code based on the clock signal and the first output clock signal.

75. 发明授权

US09629110B2 Wireless communication apparatus and method performing signal scanning to determine the strongest signal useable for stabilizing a local oscillator 有权
公开(公告)号：US09629110B2
公开(公告)日：2017-04-18
申请号：US13856269
申请日：2013-04-03
申请人： Keysight Technologies Singapore (Holdings) Pte Ltd
发明人： Steven Thompson , Henry Lee
IPC分类号： H03L7/06 , H03L7/24 , H04W56/00
CPC分类号： H04W56/0015 , H03L7/06 , H03L7/24 , Y02D70/00
摘要： Apparatus and method are provided. The solution comprises controlling (202) a receiver to scan for signals transmitted by one or more base stations; determining (204) the strongest signal of the signals found during scanning and utilizing (206) the strongest signal as a reference signal for the receiver.

76. 发明授权

US09628094B2 Apparatus and method for fast phase locking for digital phase locked loop 有权
公开(公告)号：US09628094B2
公开(公告)日：2017-04-18
申请号：US14127963
申请日：2013-09-26
申请人： INTEL CORPORATION
发明人： Amr M. Lotfy , Mohamed A. Abdelsalam , Mamdouh O. Abd El-Mejeed , Nasser A. Kurd , Mohamed A. Abdelmoneum , Mark Elzinga , Young Min Park , Jagannadha R. Rapeta , Surya Musunuri
IPC分类号： H03L7/06 , H03L7/10 , G04F10/00 , H03L7/099 , H03L7/085
CPC分类号： H03L7/105 , G04F10/005 , H03L7/085 , H03L7/0992 , H03L7/10 , H03L7/103 , H03L2207/06
摘要： Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

77. 发明授权

US09621170B2 Accurate frequency control using a MEMS-based oscillator 有权
公开(公告)号：US09621170B2
公开(公告)日：2017-04-11
申请号：US13965388
申请日：2013-08-13
申请人： Silicon Laboratories Inc.
发明人： Yunteng Huang
IPC分类号： H03L7/099 , H03L7/02 , H03L1/02 , H03L7/06
CPC分类号： H03L1/028 , H03L1/02 , H03L1/026 , H03L7/06
摘要： A micro electro mechanical system (MEMS) oscillator supplies an oscillator output signal having a first frequency that differs from a predetermined frequency of the output signal. An error determination circuit determines frequency error from the predetermined frequency based on initial frequency offset and/or temperature and provides the error information indicating a difference between the first frequency and the predetermined frequency. The error information is used by a receiving system in frequency translation logic that utilizes the oscillator output signal as a frequency reference.

78. 发明授权

US09608645B2 Phase-lock loop 有权
公开(公告)号：US09608645B2
公开(公告)日：2017-03-28
申请号：US14257796
申请日：2014-04-21
申请人： INFINEON TECHNOLOGIES AG
发明人： Chin Yeong Koh , Kar Ming Yong
IPC分类号： H03L7/06 , H03L7/095 , H03L7/099 , H03L7/113 , H03L7/18
CPC分类号： H03L7/095 , H03L7/0995 , H03L7/113 , H03L7/18 , Y10S331/02
摘要： In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal having a plurality of phases. The implementation may include comparing the output signal with the reference signal, counting falling edges about each phase of the number of phases in a predetermined time period and summing to define a count output; comparing the count output with a product of the number of phases of the output signal and the factor to define a comparison, generating a control signal based upon the comparison, and inputting the control signal to the oscillator to alter the output signal thereof.

79. 发明授权

US09602050B1 System and method for controlling a voltage controlled oscillator 有权
公开(公告)号：US09602050B1
公开(公告)日：2017-03-21
申请号：US15188010
申请日：2016-06-21
申请人： Semiconductor Components Industries, LLC
发明人： Run Levinger , Jakob Vovnoboy
IPC分类号： H03L7/06 , H03B5/12 , H03L7/089 , H03L7/093 , H03L7/099
CPC分类号： H03B5/124 , H03B5/1212 , H03B5/1243 , H03L7/0891 , H03L7/0893 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L2207/06
摘要： An electrical circuit includes: at least one inductor, at least one varactor, and at least two transistors, all of which electrically arranged to form a voltage controlled oscillator (VCO) having an oscillation frequency; wherein the at least two transistors includes a first transistor and a second transistor; wherein the first transistor has a first bulk terminal and a first parasitic diode disposed between the first bulk terminal and the first transistor; wherein the second transistor has a second bulk terminal and a second parasitic diode disposed between the second bulk terminal and the second transistor; wherein application of a first control voltage to the first bulk terminal, application of a second control voltage to the second bulk terminal, or application of first and second control voltages to the first and second bulk terminals, respectively, is effective to change the oscillation frequency of the VCO.

80. 再颁专利

USRE46336E1 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：USRE46336E1
公开(公告)日：2017-03-07
申请号：US14120258
申请日：2014-05-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00 , H03L7/06 , H03L7/08 , H03L7/081 , H03L7/087
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译：一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

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