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81. 发明授权

US09502497B2 Method for preparing power diode 有权
标题翻译：功率二极管的制作方法
公开(公告)号：US09502497B2
公开(公告)日：2016-11-22
申请号：US14902270
申请日：2014-10-22
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Genyi Wang , Xiaoshe Deng , Shengrong Zong , Dongfei Zhou
IPC分类号： H01L29/00 , H01L29/06 , H01L29/66 , H01L21/266 , H01L21/265 , H01L21/311 , H01L21/324 , H01L21/027 , H01L29/10 , H01L21/321 , H01L21/3213
CPC分类号： H01L29/0619 , H01L21/0273 , H01L21/26513 , H01L21/266 , H01L21/31116 , H01L21/32105 , H01L21/32137 , H01L21/324 , H01L29/1095 , H01L29/1608 , H01L29/20 , H01L29/2003 , H01L29/402 , H01L29/41766 , H01L29/6606 , H01L29/66136 , H01L29/66204 , H01L29/66325 , H01L29/66333 , H01L29/66719 , H01L29/66727 , H01L29/7811 , H01L29/8611
摘要： A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a terminal protecting ring; forming an oxide layer (30), knot-pushing to the terminal protecting ring; forming a gate oxide layer (60), depositing a poly-silicon layer (70) on the gate oxide layer (60); depositing a SiO2 layer (80) on the surface of the poly-silicon layer (70) and a oxide layer (50); forming a N type heavy doped region (92); forming a P+ region; removing a photoresist, implanting P type ions using the SiO2 layer (80) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (70), the gate oxide layer (60) being etched, and removing the SiO2 layer (80); and processing a front surface metallization and a back surface metallization treatment. According to the method for preparing the power diode, by adjusting the isotropy etching level of the SiO2 layer and the ion implanting dose and energy, the threshold voltage of a DMOS structure can be adjusted, and the adjustment of the forward voltage drop for the device can be achieved.
摘要翻译：一种制备功率二极管的方法，包括：提供衬底（10），在衬底（10）的前表面上生长N型层（20）; 形成端保护环; 形成氧化物层（30），向所述端子保护环打结; 形成栅极氧化物层（60），在所述栅极氧化物层（60）上沉积多晶硅层（70）。在所述多晶硅层（70）的表面和氧化物层（50）上沉积SiO 2层（80）; 形成N型重掺杂区域（92）; 形成P +区; 去除光致抗蚀剂，使用SiO 2层（80）作为掩模层注入P型离子，形成P型体区; 热退火; 在所述多晶硅层（70）的开口部形成侧壁结构，蚀刻所述栅极氧化物层（60），除去所述SiO 2层（80）。以及处理前表面金属化和背面金属化处理。根据制备功率二极管的方法，通过调整SiO2层的各向同性蚀刻水平和离子注入剂量和能量，可以调整DMOS结构的阈值电压，并调整器件的正向压降可以实现。

82. 发明申请

US20160240608A1 FIELD-STOP REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：现场停止反向导电绝缘栅双极晶体管及其制造方法
公开(公告)号：US20160240608A1
公开(公告)日：2016-08-18
申请号：US14901606
申请日：2014-06-06
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shuo ZHANG , Qiang RUI , Xiaoshe DENG , Genyi WANG
IPC分类号： H01L29/06 , H01L23/31 , H01L23/528 , H01L23/532 , H01L29/66 , H01L29/739
CPC分类号： H01L29/0607 , H01L23/3157 , H01L23/3171 , H01L23/528 , H01L23/53219 , H01L23/53247 , H01L29/0619 , H01L29/0834 , H01L29/66325 , H01L29/66333 , H01L29/7393 , H01L29/7395
摘要： A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).
摘要翻译：场阻反向导通绝缘栅双极晶体管及其制造方法。晶体管包括端子结构（200）和有源区（100）。场阻反向导通绝缘栅双极晶体管的底层是N型衬垫，衬垫的背面设置有N型电场停止层（1），电场停止层的一个表面在背衬P型结构（10）的背面设置有背面金属层（12）的背面P型结构（10）的表面。在有源区（100）中形成有从背面P型结构（10）贯穿电场停止层（1）的多个多晶硅填充结构（11）。

83. 发明申请

US20160232980A1 READOUT CIRCUIT WITH SELF-DETECTION CIRCUIT AND CONTROL METHOD THEREFOR 有权
标题翻译：具有自检电路的读出电路及其控制方法
公开(公告)号：US20160232980A1
公开(公告)日：2016-08-11
申请号：US15025846
申请日：2014-10-10
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shuming GUO , Guoyi ZONG
IPC分类号： G11C16/26 , G11C16/32 , G11C16/24
CPC分类号： G11C16/26 , G11C16/24 , G11C16/32
摘要： A readout circuit with a self-detection circuit and a control method therefor. The circuit comprises a pre-charging circuit and a control circuit, the pre-charging circuit and the control circuit being connected to a first node and used for charging a memory unit. The readout circuit also comprises a detection circuit, the detection circuit and the pre-charging circuit being connected to the first node. The detection circuit comprises a third NOT gate, a fourth NOT gate, a first NAND gate, a sixth NOT gate, a first trigger and an eighth NOT gate. In such a manner of detecting the reversal of the first NOT gate through the reversal of the third NOT gate, the charging duration of the first node (A) can be greatly reduced, thereby reducing the reading duration of the whole circuit. At the same time, the re-occurrence of a state of charging the circuit can be avoided after pre-charging has ended.
摘要翻译：一种具有自检电路及其控制方法的读出电路。该电路包括预充电电路和控制电路，预充电电路和控制电路连接到第一节点并用于对存储器单元充电。读出电路还包括检测电路，检测电路和预充电电路连接到第一节点。检测电路包括第三NOT门，第四NOT门，第一NAND门，第六NOT门，第一触发器和第八NOT门。以这样的方式，通过第三非门的反相来检测第一非门的反向，可以大大减少第一节点（A）的充电持续时间，从而减少整个电路的读取持续时间。同时，在预充电结束之后可以避免电路充电状态的再次发生。

84. 发明申请

US20160163841A1 FIELD-STOP REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：现场停止反向导电绝缘栅双极晶体管及其制造方法
公开(公告)号：US20160163841A1
公开(公告)日：2016-06-09
申请号：US14392251
申请日：2014-06-05
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shuo ZHANG , Qiang RUI , Genyi WANG , Xiaoshe DENG
IPC分类号： H01L29/739 , H01L29/08 , H01L29/66 , H01L29/49 , H01L21/02 , H01L29/417 , H01L21/311 , H01L21/265 , H01L21/324 , H01L29/423 , H01L21/285 , H01L29/40 , H01L21/28
CPC分类号： H01L29/7395 , H01L21/02164 , H01L21/26513 , H01L21/28035 , H01L21/2855 , H01L21/31116 , H01L21/324 , H01L29/0619 , H01L29/0804 , H01L29/0834 , H01L29/402 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/41708 , H01L29/42364 , H01L29/4916 , H01L29/66333
摘要： A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (12). A plurality of notches (11) which penetrate through the back-surface P-type structure (10) from the back-surface metal layer (12) to the electric field stop layer (1) are formed in the active region (100), and metals of the back-surface metal layer (12) are filled into the notches (11) to form a metal structure which extends into the electric field stop layer (1).
摘要翻译：一种场控反向导通绝缘栅双极晶体管及其制造方法。晶体管包括端子结构（200）和有源区（100）。场阻反向导通绝缘栅双极晶体管的底层是N型垫层，底层的背面设置有N型电场停止层（1），电场停止层的一个表面离开从垫层设置有背面P型结构（10），并且背面P型结构的表面设置有背面金属层（12）。在有源区域（100）中形成有从后表面金属层（12）穿过背面P型结构（10）到电场停止层（1）的多个凹口（11）并且背面金属层（12）的金属填充到凹口（11）中以形成延伸到电场停止层（1）中的金属结构。

85. 发明授权

US09093464B2 Method for fabricating small-scale MOS device 有权
标题翻译：小型MOS器件的制造方法
公开(公告)号：US09093464B2
公开(公告)日：2015-07-28
申请号：US13807306
申请日：2011-10-09
申请人： Le Wang
发明人： Le Wang
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66492 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method for fabricating a small-scale MOS device, including: preparing a substrate; forming a first trench in the substrate along a first side of the gate region and forming a second trench in the substrate along a second side of the gate region, the first side of the gate region opposite the second side of the gate region; forming a first lightly doped drain region and a second lightly doped drain region in the first trench and the second trench, respectively; forming a third trench in the substrate overlapping at least a first portion of the first lightly doped drain region and a fourth trench in the substrate overlapping at least a first portion of the second lightly doped drain region; and forming a source region and a drain region in the third trench and the fourth trench, respectively.
摘要翻译：一种制造小型MOS器件的方法，包括：制备衬底; 在所述栅极区域的第一侧沿所述衬底中形成第一沟槽，并且沿所述栅极区域的第二侧在所述衬底中形成第二沟槽，所述栅极区域的所述第一侧与所述栅极区域的第二侧相对; 在所述第一沟槽和所述第二沟槽中分别形成第一轻掺杂漏极区和第二轻掺杂漏极区; 在所述衬底中形成与所述第一轻掺杂漏极区域的至少第一部分重叠的第三沟槽和所述衬底中的与所述第二轻掺杂漏极区域的至少第一部分重叠的第四沟槽; 以及在第三沟槽和第四沟槽中分别形成源区和漏区。

86. 发明授权

US09059202B2 Metal-oxide-semiconductor (MOS) device and method for fabricating the same 有权
标题翻译：金属氧化物半导体（MOS）器件及其制造方法
公开(公告)号：US09059202B2
公开(公告)日：2015-06-16
申请号：US13807315
申请日：2011-11-30
申请人： Yan Jin
发明人： Yan Jin
IPC分类号： H01L21/02 , H01L29/66 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66477 , H01L29/42368 , H01L29/78 , H01L29/7836
摘要： A Metal-Oxide-Semiconductor (MOS) device is disclosed. The MOS device includes a substrate, a well region formed in the substrate, and a gate located on the substrate. The MOS device also includes a first lightly-doped region arranged in the well region at a first side of the gate and overlapping with the gate, and a second lightly-doped region arranged in the well region at a second side of the gate and overlapping with the gate. Further, the MOS device includes a first heavily-doped region formed in the first lightly-doped region, and a second heavily-doped region formed in the second lightly-doped region. The MOS device also includes a first high-low-voltage gate oxide boundary arranged between the first heavily-doped region and the gate, and a second high-low-voltage gate oxide boundary arranged between the second heavily-doped region and the gate. The gate covers the first high-low-voltage gate oxide boundary and the second high-low-voltage gate oxide boundary at the first side and the second side of the gate, respectively.
摘要翻译：公开了一种金属氧化物半导体（MOS）器件。 MOS器件包括衬底，形成在衬底中的阱区和位于衬底上的栅极。 MOS器件还包括布置在栅极的第一侧的阱区中并与栅极重叠的第一轻掺杂区域和布置在栅极第二侧的阱区中的第二轻掺杂区域，并且重叠与门。此外，MOS器件包括形成在第一轻掺杂区域中的第一重掺杂区域和形成在第二轻掺杂区域中的第二重掺杂区域。 MOS器件还包括布置在第一重掺杂区域和栅极之间的第一高低电压栅极氧化物边界和布置在第二重掺杂区域和栅极之间的第二高低压栅极氧化物边界。栅极分别在栅极的第一侧和第二侧覆盖第一高低压栅极氧化物边界和第二高低压栅极氧化物边界。

87. 发明授权

US08957494B2 High-voltage Schottky diode and manufacturing method thereof 有权
标题翻译：高电压肖特基二极管及其制造方法
公开(公告)号：US08957494B2
公开(公告)日：2015-02-17
申请号：US14130449
申请日：2012-10-23
申请人： CSMC Technologies FAB1 Co., Ltd.
发明人： Lihui Gu
IPC分类号： H01L29/872 , H01L29/06 , H01L29/66 , H01L29/40 , H01L29/10
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/10 , H01L29/402 , H01L29/66143 , H01L29/872
摘要： A high-voltage Schottky diode and a manufacturing method thereof are disclosed in the present disclosure. The diode includes: a P-type substrate and two N-type buried layers, a first N-type buried layer is located below a cathode lead-out area, and a second N-type buried layer is located below a cathode region; an epitaxial layer; two N-type well regions located on the epitaxial layer, a first N-type well region is a lateral drift region and it is provided with a cathode lead-out region, and a second N-type well region is located on the second N-type buried layer and it is a cathode region; a first P-type well region located on the second N-type buried layer and surrounding the cathode region; a field oxide isolation region located on the lateral drift region; an anode located on the cathode region and a cathode located on the surface of the cathode lead-out region.
摘要翻译：公开了一种高电压肖特基二极管及其制造方法。二极管包括：P型衬底和两个N型埋层，第一N型掩埋层位于阴极引出区下方，第二N型掩埋层位于阴极区下面; 外延层; 位于外延层上的两个N型阱区，第一N型阱区是横向漂移区，并具有阴极引出区，第二N型阱区位于第二N 型埋层，是阴极区; 位于所述第二N型掩埋层上并围绕所述阴极区的第一P型阱区; 位于所述横向漂移区上的场氧化物隔离区; 位于阴极区域的阳极和位于阴极引出区域的表面上的阴极。

88. 发明授权

US08956972B2 Method for manufacturing semiconductor thick metal structure 有权
标题翻译：制造半导体厚金属结构的方法
公开(公告)号：US08956972B2
公开(公告)日：2015-02-17
申请号：US14351828
申请日：2012-10-12
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： Hsiao-Chia Wu , Shilin Fang , Tse-Huang Lo , Zhengpei Chen , Shu Zhang
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/7685 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/76837 , H01L21/76838 , H01L24/03
摘要： A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.
摘要翻译：一种制造半导体厚金属结构体的方法包括厚金属沉积步骤，金属图案化步骤和钝化步骤。在厚金属沉积步骤中，使用Ti-TiN层压结构作为抗反射层，以实现无残留的4μm金属蚀刻。在金属图案化步骤中，使用N 2来保护侧壁以在接近90度的倾斜角度的4μm金属凹凸结构上实施，并且添加主过蚀刻步骤以实现侧壁的平滑度的4μm金属凹凸结构。使用半填充钝化填充结构来实现具有小于4μm的金属厚度的1.5um金属间隙的有效钝化保护。最终实现线宽/间隙为1.5μm/1.5μm的4μm厚的金属结构体的制造。

89. 发明授权

US08889535B2 Semiconductor device and method for fabricating semiconductor buried layer 有权
标题翻译：半导体器件及半导体埋层制造方法
公开(公告)号：US08889535B2
公开(公告)日：2014-11-18
申请号：US13807305
申请日：2011-09-01
申请人： Hua Song , Hsiao-Chia Wu , Tse-Huang Lo
发明人： Hua Song , Hsiao-Chia Wu , Tse-Huang Lo
IPC分类号： H01L21/425 , H01L21/265 , H01L21/74 , H01L29/02 , H01L29/08
CPC分类号： H01L21/265 , H01L21/26513 , H01L21/74 , H01L29/02 , H01L29/0821
摘要： The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects.
摘要翻译：本公开提供了半导体器件和制造半导体掩埋层的方法。该方法包括：制备包括第一氧化物层的衬底; 通过使用具有第一掩埋层区域图案的光致抗蚀剂层作为掩模，在所述基板的表面中形成第一掩埋层区域，其中所述第一掩埋层区域的掺杂状态与所述第一掩埋层区域的其他区域的掺杂状态不同基质; 在所述基板的表面和所述第一掩埋层区域上形成第二氧化物层; 以及通过使用第二氧化物层作为掩模通过自对准工艺在衬底的表面中形成第二掩埋层区域。本发明公开的方法降低了掩埋层工艺的复杂性及其成本，以及晶体缺陷的可能性。

90. 发明授权

US08836427B2 Folded cascode operational amplifier 有权
标题翻译：折叠共源共栅运算放大器
公开(公告)号：US08836427B2
公开(公告)日：2014-09-16
申请号：US13807304
申请日：2011-11-18
申请人： Liang Cheng
发明人： Liang Cheng
IPC分类号： H03F3/45 , H03F3/30
CPC分类号： H03F3/45192 , H03F3/3016 , H03F3/3028 , H03F3/45076 , H03F3/45183 , H03F2200/456 , H03F2203/45248 , H03F2203/45264 , H03F2203/45308 , H03F2203/45352 , H03F2203/45526 , H03F2203/45674 , H03F2203/45692
摘要： A folded cascode operational amplifier is disclosed. The folded cascode operational amplifier includes a first current source, a second current source, and a first voltage terminal connected to the first current source and the second current source. The folded cascode operational amplifier also includes a first input-transistor connected to the first current source in series, and a second input-transistor connected to the second current source in series. Further, the folded cascode operational amplifier includes a tail current source connected to a connection point between the first input-transistor and the second input-transistor, a load current source, and a second voltage terminal connected to the tail current source and the load current source. The folded cascode operational amplifier also includes an output-transistor connected to the load current source, and an output-terminal arranged between the second current source and the second input-transistor and connected to the output-transistor. The second current source is a mirroring current source of the first current source, and a ratio of a current passing through the second current source to a current passing through the first current source is greater than one.
摘要翻译：公开了折叠共源共栅运算放大器。折叠共源共栅运算放大器包括第一电流源，第二电流源和连接到第一电流源和第二电流源的第一电压端。折叠共源共栅运算放大器还包括串联连接到第一电流源的第一输入晶体管和串联连接到第二电流源的第二输入晶体管。此外，折叠共源共栅运算放大器包括连接到第一输入晶体管和第二输入晶体管之间的连接点的尾电流源，负载电流源和连接到尾电流源和负载电流的第二电压端资源。折叠的共源共栅运算放大器还包括连接到负载电流源的输出晶体管和布置在第二电流源和第二输入晶体管之间并连接到输出晶体管的输出端。第二电流源是第一电流源的镜像电流源，并且通过第二电流源的电流与通过第一电流源的电流的比值大于1。

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