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81. 发明授权

US09501262B2 Vectorized Galois field multiplication 有权
标题翻译：矢量化伽罗瓦域乘法
公开(公告)号：US09501262B2
公开(公告)日：2016-11-22
申请号：US14291942
申请日：2014-05-30
申请人： International Business Machines Corporation
发明人： James R. Cuffney , John G. Rell, Jr. , Eric M. Schwarz , Patrick M. West, Jr.
IPC分类号： G06F7/72
CPC分类号： G06F7/724 , G06F2207/72
摘要： Embodiments relate to vectorized Galois field multiplication. An aspect includes an input of first and second input operands of equal sizes into a single hardware tree, a calculation of a predicted parity as a parity of the first input operand ANDed with a parity of the second input operand, a comparison of the predicted parity with a parity generated on a final result of a Galois field multiplication of the first and second operands and a raising of an error based on a mismatch between the predicted parity and the generated parity.
摘要翻译：实施例涉及矢量化伽罗瓦域乘法。一方面包括将具有相同大小的第一和第二输入操作数输入到单个硬件树中，将预测奇偶校验作为第一输入操作数的奇偶校验与第二输入操作数的奇偶校验进行运算，预测奇偶校验的比较具有在第一和第二操作数的伽罗瓦域乘法的最终结果上产生的奇偶校验，以及基于预测奇偶校验和产生的奇偶校验之间的不匹配引起的误差的增加。

82. 发明申请

US20160308676A1 RSA ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
标题翻译： RSA算法加速处理器，方法，系统和指令
公开(公告)号：US20160308676A1
公开(公告)日：2016-10-20
申请号：US15102637
申请日：2013-12-28
申请人： Yang LU , Xiangzheng SUN , Nan Stan QIAO , INTEL CORPORATION
发明人： Yang Lu , Xiangzheng Sun , Nan Qiao
IPC分类号： H04L9/30 , G06F9/30 , G06F7/72
CPC分类号： H04L9/302 , G06F7/722 , G06F7/723 , G06F9/30007 , G06F9/3017 , G09C1/00
摘要： A processor includes a decode unit to decode an instruction. The instruction indicates a first 64-bit source operand having a first 64-bit value, indicates a second 64-bit source operand having a second 64-bit value, indicates a third 64-bit source operand having a third 64-bit value, and indicates a fourth 64-bit source operand having a fourth 64-bit value. An execution unit is coupled with the decode unit. The execution unit is operable, in response to the instruction, to store a result. The result includes the first 64-bit value multiplied by the second 64-bit value added to the third 64-bit value added to the fourth 64-bit value. The execution unit may store a 64-bit least significant half of the result in a first 64-bit destination operand indicated by the instruction, and store a 64-bit most significant half of the result in a second 64-bit destination operand indicated by the instruction.
摘要翻译：处理器包括解码指令译码单元。该指令指示具有第一64位值的第一64位源操作数，指示具有第二64位值的第二64位源操作数，指示具有第三64位值的第三64位源操作数，并且指示具有第四个64位值的第四个64位源操作数。执行单元与解码单元耦合。执行单元响应于该指令可操作以存储结果。结果包括第一个64位值乘以加到第四个64位值的第三个64位值的第二个64位值。执行单元可以将结果的64位最不重要的一半存储在由指令指示的第一个64位目标操作数中，并将结果的64位最高有效的一半存储在第二个64位目标操作数中，指示。

83. 发明授权

US09419793B2 Method for generating large prime number in embedded system 有权
标题翻译：在嵌入式系统中生成大量素数的方法
公开(公告)号：US09419793B2
公开(公告)日：2016-08-16
申请号：US14237363
申请日：2012-09-25
申请人： Feitian Technologies Co., Ltd.
发明人： Zhou Lu , Huazhang Yu
IPC分类号： G06F7/58 , H04L9/08 , G06F7/72
CPC分类号： H04L9/0819 , G06F7/72
摘要： A method for generating a large prime number in an embedded system, comprising: (1) setting all identifiers in an identifier group in a first storage area; generating and storing a random number with preset bit length in a third storage area; modulizing the data in the third storage area by using the data stored in the storage unit of a second storage area as a modulus; determining the serial number of the identifier to be reset in the identifier group according to the modulized value and the data in the storage unit corresponding to the modulized value; and resetting the identifier corresponding to the serial number; (2) judging whether a set identifier exists in the identifier group, if yes, then executing step (3); otherwise, returning to step (1); and (3), determining a number to be detected according to the random number and the serial number of the set identifier in the identifier group; detecting the primality of the number to be detected; if the number to be detected passes the primality detection, then outputting the number to be detected; and if the numbers to be detected corresponding to all the set identifiers in the identifier group fail to pass the primality detection, then returning to step (1). The present method has high efficiency and is suitable for an embedded system.
摘要翻译：一种用于在嵌入式系统中生成大素数的方法，包括：（1）在第一存储区域中设置标识符组中的所有标识符; 在第三存储区域中生成并存储具有预设位长度的随机数; 通过使用存储在第二存储区域的存储单元中的数据作为模数来对第三存储区域中的数据进行模块化; 根据所述调制值和对应于所述模拟值的所述存储单元中的数据，确定所述标识符组中要重置的标识符的序列号; 并重新设置与序列号对应的标识符; （2）判断标识符组中是否存在集合标识符，如果是，则执行步骤（3）; 否则返回步骤（1）; 和（3）根据标识符组中的设置标识符的随机数和序列号来确定要检测的数量; 检测要检测的号码的原始性; 如果要检测的号码通过原色检测，则输出要检测的号码; 并且如果与标识符组中的所有集合标识符相对应的要检测的号码不能通过原色检测，则返回到步骤（1）。本方法效率高，适用于嵌入式系统。

84. 发明授权

US09419789B2 Method and apparatus for scalar multiplication secure against differential power attacks 有权
标题翻译：用于标量乘法的方法和装置防止差动电力攻击
公开(公告)号：US09419789B2
公开(公告)日：2016-08-16
申请号：US14384458
申请日：2014-09-05
申请人： UMM AL-QURA UNIVERSITY
发明人： Turki F Al-Somani , Hilal Houssain
IPC分类号： H04L9/00 , H04L9/30 , G06F7/72
CPC分类号： H04L9/003 , G06F7/725 , G06F2207/7223 , G06F2207/7252 , H04L9/3066
摘要： A method of scalar multiplication to obtain the scalar product between a key and a point on an elliptic curve, wherein the secret is m bits long. In selected embodiments, the first step is to partition the secret into two partitions each with m/2 bits. Point-doubling operations are performed on the point and stored into three buffers. Point additions are performed at randomized time intervals thereby preventing the method from being susceptible to differential power analysis attacks.
摘要翻译：一种标量乘法的方法来获得椭圆曲线上的一个键和一个点之间的标量乘积，其中秘密是m位长。在所选择的实施例中，第一步是将秘密划分成两个具有m / 2比特的分区。点加倍操作在点上执行并存储在三个缓冲区中。以随机时间间隔执行点加法，从而防止该方法易受差分功率分析攻击的影响。

85. 发明授权

US09417848B2 Serial multiply accumulator for galois field 有权
标题翻译：用于伽罗瓦域的串行乘法累加器
公开(公告)号：US09417848B2
公开(公告)日：2016-08-16
申请号：US14228763
申请日：2014-03-28
申请人： Storart Technology Co., Ltd.
发明人： Jui Hui Hung , Chih Nan Yen
IPC分类号： G06F7/72 , G06F7/544
CPC分类号： G06F7/724 , G06F7/5443
摘要： A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.
摘要翻译：公开了用于在Galois域上进行两次乘法和一次加法的串行乘法累加器（MAC）。 MAC包括第一元件供给电路，第二元件馈送电路，多个第一计算电路和第二计算电路。通过重新布置电路设计，可以节省常规MAC中使用的许多元件，如XOR门和寄存器。本发明具有面积成本较低的优点。

86. 发明授权

US09405511B2 S12 TX FIR architecture 有权
标题翻译： S12 TX FIR架构
公开(公告)号：US09405511B2
公开(公告)日：2016-08-02
申请号：US14524774
申请日：2014-10-27
申请人： STMICROELECTRONICS (CANADA), INC. , STMICROELECTRONICS S.r.l.
发明人： John Hogeboom , Hock Khor , Matteo Alessio Traldi , Anton Pelteshki
IPC分类号： H03H7/06 , G06F7/72 , H03H17/06 , G06F5/16 , H04L25/02
CPC分类号： G06F7/724 , G06F5/16 , H03H17/06 , H04L25/0272 , H04L25/0288
摘要： A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.
摘要翻译： FIR发送架构使用多个驱动器分区，以允许具有不同延迟的信号被驱动器自身求和到输出信号中。该架构包括第一多路复用器，多个延迟单元，多个符号块，开关块，第二多路复用器和多个驱动器。

87. 发明授权

US09391773B2 Elliptic curve point multiplication procedure resistant to side-channel information leakage 有权
标题翻译：椭圆曲线点乘法程序抗侧信道泄漏
公开(公告)号：US09391773B2
公开(公告)日：2016-07-12
申请号：US14245732
申请日：2014-04-04
申请人： QUALCOMM Incorporated
发明人： David Merrill Jacobson , Billy Bob Brumley
IPC分类号： H04L9/30 , G06F7/72 , H04L9/00
CPC分类号： H04L9/3066 , G06F7/725 , G06F2207/7257 , H04L9/003 , H04L2209/24 , H04L2209/72
摘要： One feature pertains to elliptic curve (EC) point multiplication for use in generating digital signatures. In one aspect, a scalar multiplier (k) of a base point (P) of order (n) is selected on an elliptic curve for use with EC point multiplication. An integer value (r) is then randomly generated from within a range of values constrained so that, regardless of the particular value of (r) obtained within the range, EC point multiplication procedures performed using the scalar multiplier (k) summed with a product of the integer multiplier (r) and the order (n) consume device resources independent of the value of the scalar multiplier (k) to thereby reduce or eliminate side-channel leakage. This may be achieved by determining the range of values for r so that the bit position of the most significant bit of k+(r*n) will be even and fixed for a particular elliptic curve.
摘要翻译：一个特征涉及用于生成数字签名的椭圆曲线（EC）点乘法。在一个方面，在椭圆曲线上选择阶数（n）的基点（P）的标量乘数（k），以用于EC点乘法。然后从受限制的值的范围内随机生成整数值（r），使得不管在该范围内获得的（r）的特定值，使用与乘积相加的标量乘数（k）执行的EC点乘法程序整数乘法器（r）和顺序（n）消耗与标量乘法器（k）的值无关的设备资源，从而减少或消除侧信道泄漏。这可以通过确定r的值的范围来实现，使得对于特定的椭圆曲线，k +（r * n）的最高有效位的位位置将是均匀和固定的。

88. 发明授权

US09389835B2 Finite field inverter 有权
标题翻译：有限域逆变器
公开(公告)号：US09389835B2
公开(公告)日：2016-07-12
申请号：US14236336
申请日：2012-12-05
申请人： SOUTH CHINA UNIVERSITY OF TECHNOLOGY
发明人： Shaohua Tang , Haibo Yi
IPC分类号： G06F7/00 , G06F7/72
CPC分类号： G06F7/726
摘要： A finite field inverter is disclosed, wherein the finite field inverter includes an input port, an output port and a search tree inverse circuit configured to perform an inverse operation of the operand a(x) in the finite field GF(2n) based on a search tree structure. The search tree inverse circuit is provided with a left search tree and a right search tree. The left search tree and the right search tree each includes tree nodes for processing inverse operations over the finite field GF(2n) and connecting wires connected between the tree nodes. The tree nodes include a root node, internal nodes and leaf nodes. Each path from the root node to a leaf node represents an element in the finite field GF(2n). The connecting wires between the tree nodes connect the path representing the operand a(x) with the path representing the inversion result b(x) . The present invention uses a search tree inverse circuit to achieve an inverse operation of an element in a finite field, and compared with the existing finite field inverter, the present invention is more efficient in processing inverse operations over the finite field GF(2n).
摘要翻译：公开了一种有限域逆变器，其中有限域逆变器包括一个输入端口，一个输出端口和一个搜索树反向电路，被配置为基于一个有限域GF（2n）执行操作数a（x）的逆运算搜索树结构。搜索树反向电路具有左搜索树和右搜索树。左搜索树和右搜索树各自包括用于处理有限域GF（2n）上的逆运算的树节点和连接在树节点之间的连接线。树节点包括根节点，内部节点和叶节点。从根节点到叶节点的每条路径都表示有限域GF（2n）中的一个元素。树节点之间的连接线将表示操作数a（x）的路径与表示反演结果b（x）的路径相连。本发明使用搜索树反向电路来实现有限域中的元素的逆运算，并且与现有的有限域逆变器进行比较，本发明在有限域GF（2n）处理逆运算方面更有效。

89. 发明授权

US09300472B2 Method and apparatus for improving digital signatures 有权
标题翻译：改进数字签名的方法和装置
公开(公告)号：US09300472B2
公开(公告)日：2016-03-29
申请号：US13249710
申请日：2011-09-30
申请人： Sampo Sovio , Martti Takala , Rauno Tamminen , Suvi Lehtinen
发明人： Sampo Sovio , Martti Takala , Rauno Tamminen , Suvi Lehtinen
IPC分类号： H04L9/32 , G06F7/58 , G06F7/72 , G06F1/26 , G08B13/00 , G08B29/00 , H04N1/44
CPC分类号： H04L9/3247 , G06F7/582 , G06F7/725 , H04L9/3252 , H04L2209/805
摘要： Systems and methods are provided for enchancing pseudo random number generation to thwart various security attacks to a system that relies on digital signature security measures. For example, a random number may be bound to a message that is to be signed using a digital signature. Alternatively, a random number may be bound to a secret seed value, which may be updated subsequent to each signing. Alternatively still, a random number may be bound to both the message to be signed using a digital signature and a secret seed value.
摘要翻译：提供了系统和方法，用于加强伪随机数生成，以阻止各种安全攻击到依赖于数字签名安全措施的系统。例如，随机数可以绑定到要使用数字签名签名的消息。或者，随机数可以绑定到秘密种子值，其可以在每次签名之后被更新。或者，仍然可以使用数字签名和秘密种子值将随机数绑定到要签名的消息。

90. 发明授权

US09268564B2 Vector and scalar based modular exponentiation 有权
标题翻译：基于矢量和标量的模幂
公开(公告)号：US09268564B2
公开(公告)日：2016-02-23
申请号：US13994717
申请日：2012-05-30
申请人： Shay Gueron , Vlad Krasnov
发明人： Shay Gueron , Vlad Krasnov
IPC分类号： G06F7/72 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/723 , G06F2207/3828
摘要： An embodiment includes a method for computing operations, such as modular exponentiation, using a mix of vector and scalar instructions to accelerate various applications such as encryption protocols that rely heavily on large number arithmetic operations. The embodiment requires far fewer instructions to execute the operations than more conventional practices. Other embodiments are described herein.
摘要翻译：一个实施例包括一种用于计算操作（诸如模幂运算）的方法，其使用向量和标量指令的混合来加速各种应用，例如严重依赖于大量算术运算的加密协议。与更常规的做法相比，该实施例需要执行操作的指令要少得多。本文描述了其它实施例。

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