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81. 发明授权

US09590641B2 Semiconductor apparatus and regulation circuit thereof 有权
标题翻译：半导体装置及其调节电路
公开(公告)号：US09590641B2
公开(公告)日：2017-03-07
申请号：US14458355
申请日：2014-08-13
申请人： SK hynix Inc.
发明人： Young Suk Seo , Da In Im
IPC分类号： H03L7/06 , H03L7/085 , H03L7/081
CPC分类号： H03L7/085 , H03L7/0814
摘要： A regulation circuit of a semiconductor apparatus includes a control block configured to generate control signals in response to a reference clock signal and a feedback clock signal; and a noise compensation block configured to compensate for a variation in a level of power in response to the control signals.
摘要翻译：半导体装置的调节电路包括：控制块，被配置为响应于参考时钟信号和反馈时钟信号产生控制信号; 以及噪声补偿块，被配置为响应于所述控制信号来补偿功率电平的变化。

82. 发明授权

US09590572B2 Logarithmic detector amplifier system for use as high sensitivity selective receiver without frequency conversion 有权
标题翻译：对数检波器放大器系统用作高灵敏度选择接收器，无需频率转换
公开(公告)号：US09590572B2
公开(公告)日：2017-03-07
申请号：US14216945
申请日：2014-03-17
申请人： DockOn AG
发明人： Patrick Antoine Rada , Forrest James Brown , Alexandre Dupuy
IPC分类号： H04B1/16 , H03F3/193 , H03F1/56 , H03F3/195 , H04B1/22 , H03L7/06
CPC分类号： H03F3/193 , H03F1/38 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/129 , H03F2200/147 , H03F2200/222 , H03F2200/237 , H03F2200/241 , H03F2200/243 , H03F2200/246 , H03F2200/261 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/309 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/402 , H03F2200/438 , H03F2200/451 , H03F2200/462 , H03L7/06 , H04B1/22
摘要： A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.
摘要翻译：提供对数检波器放大（LDA）系统用作高灵敏度接收增强器或替代通信设备的接收链中的低噪声放大器。 LDA系统包括放大电路，其被配置为接收具有第一频率的输入信号并基于输入信号产生振荡;采样电路，耦合到放大电路并且被配置为基于预定阈值终止振荡以周期性地钳位和重新启动振荡以产生由振荡和输入信号调制的一系列脉冲，以及一个或多个谐振电路，与放大电路耦合并被配置成建立操作频率并产生具有第二频率的输出信号，第二频率与第一频率基本相同。

83. 发明授权

US09584105B1 Timing generator for generating high resolution pulses having arbitrary widths 有权
标题翻译：用于产生具有任意宽度的高分辨率脉冲的定时发生器
公开(公告)号：US09584105B1
公开(公告)日：2017-02-28
申请号：US15066182
申请日：2016-03-10
申请人： ANALOG DEVICES, INC.
发明人： David P. Foley
IPC分类号： H03L7/06 , H03K5/13 , H03L7/08 , H03K5/00
CPC分类号： H03K5/133 , H03K5/134 , H03K2005/00019 , H03K2005/00065 , H03L7/0816
摘要： An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate a fine delayed rising edge signal from the coarse delayed rising edge signal and a fine delayed falling edge signal from the coarse delayed falling edge signal; an edge combiner configured to generate the timing signal based on the fine delayed rising edge signal and the fine delayed falling edge signal; and a masking circuit configured to generate a rising edge masking signal and a falling edge masking signal for controlling when the rising edges and the falling edges of the timing signal are generated.
摘要翻译：示例性定时发生器包括：粗延迟电路，被配置为从参考定时信号产生粗延迟上升沿信号和粗延迟下降沿信号; 配置为从粗延迟上升沿信号和粗延迟下降沿信号产生精细延迟下降沿信号的精细延迟上升沿信号; 边缘组合器，被配置为基于所述精细延迟上升沿信号和精细延迟下降沿信号产生定时信号; 以及掩蔽电路，被配置为产生上升沿屏蔽信号和下降沿屏蔽信号，用于控制何时产生定时信号的上升沿和下降沿。

84. 发明授权

US09571105B2 System and method for an accuracy-enhanced DLL during a measure initialization mode 有权
标题翻译：测量初始化模式期间精度增强型DLL的系统和方法
公开(公告)号：US09571105B2
公开(公告)日：2017-02-14
申请号：US14566358
申请日：2014-12-10
申请人： Micron Technology, Inc.
发明人： Jongtae Kwak
IPC分类号： H03L7/06 , H03L7/08 , G11C7/10 , G11C7/22 , H03L7/081
CPC分类号： H03L7/0802 , G11C7/1072 , G11C7/222 , H03L7/0814 , H03L7/0818
摘要： A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.
摘要翻译：一种具有延迟锁定环路和延迟控制电路的时钟发生器。延迟锁定环接收输入时钟信号并调整可调延迟电路以产生与接收的输入时钟信号同步的输出时钟信号。耦合到延迟锁定环的延迟控制电路在比较输入时钟信号和输出时钟信号的相位差之后，产生控制信号以初始化延迟测量操作以调整可调延迟电路。延迟控制电路还产生开始测量控制信号，以开始测量延迟通过可调延迟电路传播的测量信号的延迟，并产生停止测量控制信号以停止测量信号的延迟测量。然后调整延迟锁定环路的延迟调整，以在同步输入和输出时钟信号时应用延迟测量。

85. 发明授权

US09571080B2 Delay-locked loop arrangement and method for operating a delay-locked loop circuit 有权
标题翻译：延迟锁定环路布置和操作延迟锁定环路的方法
公开(公告)号：US09571080B2
公开(公告)日：2017-02-14
申请号：US14817446
申请日：2015-08-04
申请人： Synopsys, Inc.
发明人： Jan Grabinski
IPC分类号： H03L7/06 , H03K5/135 , H03L7/08 , H03L7/081 , H03L7/10 , H03K5/00
CPC分类号： H03K5/135 , H03K2005/00058 , H03L7/08 , H03L7/0802 , H03L7/0812 , H03L7/10
摘要： Delay-locked loop arrangement comprising a steering unit and a delay-locked loop circuit. The steering unit is configured to generate a reference clock signal and a main clock signal wherein the reference clock signal and the main clock signal feature a first frequency during a performance mode of operation. The reference clock signal and the main clock signal feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation. The delay-locked loop circuit is configured to generate an error signal depending on a comparison of the reference clock signal and a feedback signal. Furthermore, the delay-locked loop circuit generates the feedback signal depending on the error signal and on the main clock signal.
摘要翻译：延迟锁定环路布置包括转向单元和延迟锁定环路电路。转向单元被配置为产生参考时钟信号和主时钟信号，其中参考时钟信号和主时钟信号在执行操作模式期间具有第一频率。参考时钟信号和主时钟信号在睡眠操作模式期间具有低于第一频率的第二频率和相对于彼此的相位延迟。延迟锁定环电路被配置为根据参考时钟信号和反馈信号的比较产生误差信号。此外，延迟锁定环电路根据误差信号和主时钟信号产生反馈信号。

86. 发明授权

US09559703B2 System ready in a clock distribution chip 有权
标题翻译：系统准备在时钟分配芯片中
公开(公告)号：US09559703B2
公开(公告)日：2017-01-31
申请号：US14613123
申请日：2015-02-03
申请人： Hittite Microwave Corporation
发明人： Tunc Mahmut Cenger , Gordon John Allan
IPC分类号： H03L7/06 , H03L7/08 , G06F1/10 , G06F1/06 , H04L12/64
CPC分类号： H03L7/08 , G06F1/06 , G06F1/10 , H04L12/6418
摘要： Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready.
摘要翻译：本文提供了用于在时钟分配芯片或系统中准备的系统的装置和方法。在某些配置中，通信系统包括具有分频器和相位控制电路以提供输出时钟信号的时钟产生电路。通信系统还包括系统就绪电路，以提供指示所有输出时钟信号是否准备就绪的系统就绪信号。

87. 发明授权

US09553570B1 Crystal-less jitter attenuator 有权
标题翻译：无晶振抖动衰减器
公开(公告)号：US09553570B1
公开(公告)日：2017-01-24
申请号：US14566571
申请日：2014-12-10
申请人： Integrated Device Technology, Inc.
发明人： Jagdeep Bal
IPC分类号： H03L7/06 , H03K5/1252 , H03B5/08 , H03B5/04
CPC分类号： H03K5/1252 , H03B5/04 , H03B5/1212 , H03B5/124 , H03B2200/009
摘要： An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.
摘要翻译：用于从时钟信号中去除抖动的集成电路包括集成电路管芯。集成电路管芯包括信号比较器。信号比较器被配置为确定抖动输入时钟信号和校正信号之间的频率差。数字低通滤波器被耦合以接收和滤除频率差并提供经滤波的输出信号。自由运行的无晶体振荡器产生参考信号。分数输出分频器耦合到自由运行的无晶体振荡器和数字低通滤波器。分数输出分频器利用滤波后的输出信号建立一个值，以分配参考信号以获得干净的输出时钟信号。干净的输出时钟信号反馈到信号比较器，并用作校正信号。

88. 发明授权

US09543969B2 High-speed resistor-based charge pump for active loop filter-based phase-locked loops 有权
标题翻译：基于高速电阻器的电荷泵，用于基于有源环路滤波器的锁相环
公开(公告)号：US09543969B2
公开(公告)日：2017-01-10
申请号：US14961590
申请日：2015-12-07
申请人： Texas Instruments Incorporated
发明人： Vishnu Ravinuthula , Kenneth George Maclean
IPC分类号： H03L7/06 , H03L7/085
CPC分类号： H03L7/085 , H03L7/0891
摘要： Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in a charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.
摘要翻译：描述了用于增加用于基于有源环路滤波器的锁相环（PLL）的基于电阻器的电荷泵的速度的技术。这些技术可以包括将电流源的各个节点之间的低电阻放电路径放置在电荷泵中，并且在电荷泵关闭时选择性地启动低电阻放电路径。低电阻放电路径可以具有低于电荷泵中的各个节点之间的其它电流路径的电阻的电阻（例如，由电荷源的电流源和电荷泵中的电阻器形成的电流路径），从而减少当电荷泵关闭时复位各个节点上的电荷所需的时间量。以这种方式，可以增加基于电阻器的电荷泵的速度，从而允许基于有源滤波器的PLL的总体速度增加。

89. 发明授权

US09537493B2 Phase lock loop circuit having a wide bandwidth 有权
标题翻译：具有宽带宽的锁相环电路
公开(公告)号：US09537493B2
公开(公告)日：2017-01-03
申请号：US14283702
申请日：2014-05-21
申请人： Robert Bosch GmbH
发明人： Ganesh K. Balachandran , Vladimir P. Petkov
IPC分类号： H03L7/06 , H03L7/093 , H03L7/099 , H03L7/085
CPC分类号： H03L7/093 , H03L7/085 , H03L7/099
摘要： A phase lock loop circuit includes a phase detector, loop filter, voltage controlled oscillator, and a divider. The divider includes a controller and a memory that stores a lookup table of signal levels for a sinusoidal feedback signal. The divider receives an output signal from the voltage controlled oscillator and generates an output signal corresponding to the values in the lookup table in a predetermined order to generate a sinusoidal feedback signal. The divider generates a new output for each cycle of the output signal from the voltage controlled oscillator and enables PLL bandwidth that meets or exceeds a frequency of the reference signal.
摘要翻译：锁相环电路包括相位检测器，环路滤波器，压控振荡器和分频器。分频器包括控制器和存储器，其存储用于正弦反馈信号的信号电平的查找表。分压器接收来自压控振荡器的输出信号，并以预定的顺序产生与查找表中的值对应的输出信号，以产生正弦反馈信号。分压器为来自压控振荡器的输出信号的每个周期产生一个新的输出，并使得能够达到或超过参考信号频率的PLL带宽。

90. 发明授权

US09537492B2 Sampled analog loop filter for phase locked loops 有权
标题翻译：用于锁相环的采样模拟环路滤波器
公开(公告)号：US09537492B2
公开(公告)日：2017-01-03
申请号：US14745017
申请日：2015-06-19
申请人： ANALOG DEVICES, INC.
发明人： Alexander A. Alexeyev , Eric G. Nestler
IPC分类号： H03L7/06 , H03L7/085
CPC分类号： H03L7/085
摘要： An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.
摘要翻译：集成电路实现了锁相环（PLL）的至少一部分。集成电路包括用于PLL的采样模拟环路滤波器。环路滤波器包括用于接收表示参考时钟信号和第一时钟信号之间的相位差的信号的第一输入端，用于提供用于控制振荡器频率的频率控制信号的第一输出端，用于接收振荡器的时钟输入环路定时时钟信号，用于控制环路滤波器的操作定时;以及数字控制输入，用于根据多个控制值配置环路滤波器的响应。在一些示例中，环路滤波器包括通过可控开关耦合的电荷存储元件和用于在电荷存储元件之间传送电荷的控制电路，以产生环路滤波器的配置响应。

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