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1. 发明申请

US20150222273A1 APPARATUS AND METHODS FOR PHASE-LOCKED LOOPS WITH SOFT TRANSITION FROM HOLDOVER TO REACQUIRING PHASE LOCK 有权
标题翻译：用于从保持软件过渡到相位锁定的相位锁定鞋的装置和方法
公开(公告)号：US20150222273A1
公开(公告)日：2015-08-06
申请号：US14610025
申请日：2015-01-30
申请人： Hittite Microwave Corporation
发明人： Gordon John Allan , Justin L. Fortier
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , H03L7/10 , H03L7/101 , H03L7/14 , H03L7/143 , H03L7/146 , H03L7/23
摘要： Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.
摘要翻译：本文提供了锁相环（PLL）的装置和方法。在某些配置中，时钟系统包括PLL，控制电路和保持电路，其经由保持开关和可变电阻器电耦合到PLL的环路滤波器的输入。控制电路基于所选择的参考时钟信号产生用于PLL的输入时钟信号。当控制电路确定所选择的参考时钟信号不可靠时，控制电路将禁用PLL的反馈回路并打开保持开关。在所选择的参考时钟信号改变或变得可靠之后，控制电路在保持保持开关导通的同时启用PLL的反馈环路，并且随着时间的推移控制可变电阻器的电阻以提供从保持到重新获取锁相的软转换。

2. 发明授权

US08981861B2 Injection locked pulsed oscillator 有权
标题翻译：注入锁定脉冲振荡器
公开(公告)号：US08981861B2
公开(公告)日：2015-03-17
申请号：US13827225
申请日：2013-03-14
申请人： Hittite Microwave Corporation
发明人： Cemin Zhang , Christopher T. Lyons
IPC分类号： H03L7/24 , H03B5/12 , H03L7/00
CPC分类号： H03L7/00 , H03B5/1218 , H03B2200/0074 , H03L7/24
摘要： An injection locked pulsed oscillator includes a voltage controlled oscillator (VCO) responsive to an injection signal. The injection locked pulsed oscillator includes at least one enable circuit responsive to a first enable signal to enable output pulses from the VCO. The injection locked pulsed oscillator also includes timing circuit responsive to a pulse repetition frequency signal and is configured to provide the injection signal to phase lock the VCO and provide the first enable signal delayed from the injection signal to shape a width of the output pulses from the VCO.
摘要翻译：注入锁定脉冲振荡器包括响应于注入信号的压控振荡器（VCO）。注入锁定脉冲振荡器包括响应于第一使能信号的至少一个使能电路以使能来自VCO的输出脉冲。注入锁定脉冲振荡器还包括响应于脉冲重复频率信号的定时电路，并且被配置为提供注入信号以锁相VCO并提供从注入信号延迟的第一使能信号，以形成来自 VCO。

3. 发明授权

US08937514B2 Local oscillator (LO) driver circuit for a mixer 有权
标题翻译：用于混频器的本地振荡器（LO）驱动电路
公开(公告)号：US08937514B2
公开(公告)日：2015-01-20
申请号：US13761672
申请日：2013-02-07
申请人： Hittite Microwave Corporation
发明人： B. Tarik Cavus , Abdullah Celebi
IPC分类号： H03L5/00 , H04B1/40 , G06F1/00 , H03D7/14
CPC分类号： H03L5/00 , G06F1/00 , H03D7/1441 , H03D7/1458 , H04B1/40
摘要： An improved local oscillator (LO) driver circuit for a mixer, the LO driver circuit includes a gain circuit responsive to LO input signals at a predetermined LO frequency range. At least a first pair of a parallel combination of a resistor and a capacitor is coupled to the gain circuit and to LO inputs of the mixer. The resistor configured to increase impedance at low frequencies of the frequency range and the capacitor is configured to reduce the impedance of the first parallel combination at high frequencies of the frequency range to reduce resistive impendence of the resistor. At least a second pair of a parallel combination of a low quality factor inductor and a high quality factor inductor is connected to the first pair. The second pair in serial combination with the first pair is tuned to provide a constant desired load impedance and a constant desired voltage swing at the LO inputs of the mixer over the predetermined LO frequency range.
摘要翻译：用于混频器的改进的本地振荡器（LO）驱动器电路，LO驱动器电路包括响应于预定LO频率范围的LO输入信号的增益电路。电阻器和电容器的并联组合的至少第一对耦合到增益电路和混频器的LO输入端。被配置为增加频率范围的低频阻抗的电阻器和电容器被配置为在频率范围的高频下降低第一并联组合的阻抗，以减小电阻器的阻抗阻抗。低质量因子电感器和高品质因数电感器的至少第二对并联组合被连接到第一对。与第一对串联组合的第二对被调谐以在预定的LO频率范围上提供恒定的期望的负载阻抗和在混频器的LO输入处的恒定的期望电压摆幅。

4. 发明授权

US08742846B1 Selectable gain differential amplifier 有权
标题翻译：可选增益差分放大器
公开(公告)号：US08742846B1
公开(公告)日：2014-06-03
申请号：US13827105
申请日：2013-03-14
申请人： Hittite Microwave Corporation
发明人： Seth L. Everton
IPC分类号： H03F3/45
CPC分类号： H03F3/45089 , H03F3/72 , H03F2203/45302 , H03F2203/45318 , H03F2203/45392 , H03F2203/45396 , H03G1/0023 , H03G1/0088
摘要： The selectable gain differential amplifier includes a differential amplifier, a plurality of cascade leg pairs connected to the differential amplifier, each leg of each cascode pair including a cascode device and a load resistor configured to provide a selectable gain. A variable voltage generator is connected to each leg configured to set gain resistor voltage of any active cascode leg pair to a uniform predetermined common mode voltage and the output node voltage of any inactive cascode leg pair to a voltage different from the predetermined common mode voltage. A selector circuit is configured to select the output of any said cascode leg pair.
摘要翻译：可选择的增益差分放大器包括差分放大器，连接到差分放大器的多个级联支路对，每个共源共栅对的每个支路包括共源共用器件和被配置为提供可选增益的负载电阻器。可变电压发生器被连接到每个支路，其被配置为将任何有源共源共享支路对的增益电阻器电压设置为均匀的预定共模电压，并且将任何非活动共源共享线对的输出节点电压设置为不同于预定共模电压的电压。选择器电路被配置为选择任何所述共源共享线对对的输出。

5. 发明授权

US09425752B2 Distributed amplifier with improved stabilization 有权
标题翻译：分布式放大器具有改进的稳定性
公开(公告)号：US09425752B2
公开(公告)日：2016-08-23
申请号：US14327944
申请日：2014-07-10
申请人： Hittite Microwave Corporation
发明人： Keith Benson
IPC分类号： H03F3/193 , H03F1/08 , H03F1/22 , H03F3/60
CPC分类号： H03F1/18 , H03F1/086 , H03F1/223 , H03F1/42 , H03F3/19 , H03F3/193 , H03F3/607 , H03F2200/108 , H03F2200/144 , H03F2200/153 , H03F2200/267 , H03F2200/423 , H03F2200/61
摘要： A distributed amplifier with improved stabilization includes an input transmission circuit, an output transmission circuit, at least one cascade amplifier coupled between said input and output transmission circuits. Each cascade amplifier includes a common-gate configured transistor coupled to the output transmission circuit, and a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor. The distributed amplifier also includes a non-parasitic resistance and capacitance coupled in series between a drain and a gate of at least one of the common-gate configured transistors for increasing the amplifier stability.
摘要翻译：具有改进的稳定性的分布式放大器包括输入传输电路，输出传输电路，耦合在所述输入和输出传输电路之间的至少一个级联放大器。每个级联放大器包括耦合到输出传输电路的共栅配置的晶体管，以及耦合在输入传输电路和共栅配置晶体管之间的公共源配置的晶体管。分布式放大器还包括串联耦合在至少一个共栅配置晶体管的漏极和栅极之间的非寄生电阻和电容，用于增加放大器的稳定性。

6. 发明申请

US20140320173A1 FRACTIONAL PHASE LOCKED LOOP HAVING AN EXACT OUTPUT FREQUENCY AND PHASE AND METHOD OF USING THE SAME 审中-公开
标题翻译：具有精确输出频率和相位的相位锁相环及其使用方法
公开(公告)号：US20140320173A1
公开(公告)日：2014-10-30
申请号：US14329293
申请日：2014-07-11
申请人： Hittite Microwave Corporation
发明人： Mark M. Cloutier , Gord Allan , Tudor Lipan
IPC分类号： H03L7/197
CPC分类号： H03L7/1976 , H03L7/0994
摘要： A fractional-N frequency synthesizer having an exact output frequency and phase includes a phase locked loop including a phase detector responsive to a reference signal and a fractional divider. The phase locked loop has an output signal whose frequency is a fractional multiple of the input reference signal. The synthesizer also includes a modulator having a modulus for providing an output to the fractional divider, in which the modulus multiplied by the ratio of the frequency of the output signal to the frequency of the reference signal is a non-integer number.
摘要翻译：具有精确输出频率和相位的分数N频率合成器包括锁相环，其包括响应于参考信号的相位检测器和分数分频器。锁相环具有输出信号，其频率是输入参考信号的分数倍。合成器还包括具有用于向分数分频器提供输出的模数的调制器，其中模数乘以输出信号的频率与参考信号的频率的比率是非整数。

7. 发明申请

US20140269665A1 Fast Turn On System For A Synthesized Source Signal 有权
标题翻译：快速打开合成源信号的系统
公开(公告)号：US20140269665A1
公开(公告)日：2014-09-18
申请号：US13833324
申请日：2013-03-15
申请人： Hittite Microwave Corporation
发明人： Mark M. Cloutier , Greg Bachmanek , Tolga Pamir
IPC分类号： H04J3/06
CPC分类号： H03L7/00 , H03F1/30 , H03F3/00 , H03F3/195 , H03F3/45475 , H03F3/72 , H03F2200/451 , H03F2200/453 , H03F2200/459 , H03G3/348
摘要： A fast turn on compensation system for a synthesized signal source includes a synthesized signal source coupled to a power supply and configured to generate a phase stable radio frequency (RF) output signal. A mute amplifier is coupled to the synthesized signal source and the power supply. A dummy amplifier is coupled to the mute amplifier and the power supply. A mute controller is coupled to the mute amplifier and the dummy amplifier, the mute controller is responsive to an enable signal and configured to enable the dummy amplifier and disable the mute amplifier when no RF output signal is being generated and disable the dummy amplifier and enable the mute amplifier when the RF output signal is being generated such that total power supply current delivered to the synthesized signal source and the dummy amplifier or mute amplifier is approximately constant before, during, and after enabling the mute amplifier to reduce phase disturbance of the RF output signals.
摘要翻译：用于合成信号源的快速启动补偿系统包括耦合到电源并被配置为产生相位稳定射频（RF）输出信号的合成信号源。静音放大器耦合到合成信号源和电源。虚拟放大器耦合到静音放大器和电源。静音控制器耦合到静音放大器和虚拟放大器，静音控制器响应于使能信号，并配置为使能虚拟放大器，并且在没有产生RF输出信号时禁用静音放大器，并禁用虚拟放大器并使能静音放大器当RF输出信号被产生时，使得在使能静音放大器减少RF的相位扰动之前，期间和之后传送到合成信号源和虚拟放大器或静音放大器的总电源电流几乎恒定输出信号。

8. 发明申请

US20140266466A1 Internally, Resistively, Sensed Darlington Amplifier 有权
标题翻译：内部，电阻式，感应达林顿放大器
公开(公告)号：US20140266466A1
公开(公告)日：2014-09-18
申请号：US13827139
申请日：2013-03-14
申请人： Hittite Microwave Corporation
发明人： Joseph Cuggino
IPC分类号： H03F3/19
CPC分类号： H03F3/195 , H03F1/302 , H03F3/19 , H03F2200/555 , H03F2200/93
摘要： An internally, resistively, sensed Darlington amplifier includes a Darlington amplifier, at least an input transistor, an output transistor, a resistive divider, a signal input node, and a signal output node. The Darlington amplifier is responsive to an input signal and configured to generate an output signal. An internal bias setting resistor is coupled between the signal output node, a collector of the output transistor, and the resistive divider. The bias setting resistor is configured to set and regulate the bias current of the Darlington amplifier.
摘要翻译：内部，电阻感应的达林顿放大器包括达林顿放大器，至少输入晶体管，输出晶体管，电阻分压器，信号输入节点和信号输出节点。达林顿放大器响应于输入信号并被配置为产生输出信号。内部偏置设置电阻耦合在信号输出节点，输出晶体管的集电极和电阻分压器之间。偏置设置电阻器被配置为设置和调节达林顿放大器的偏置电流。

9. 发明授权

US09559703B2 System ready in a clock distribution chip 有权
标题翻译：系统准备在时钟分配芯片中
公开(公告)号：US09559703B2
公开(公告)日：2017-01-31
申请号：US14613123
申请日：2015-02-03
申请人： Hittite Microwave Corporation
发明人： Tunc Mahmut Cenger , Gordon John Allan
IPC分类号： H03L7/06 , H03L7/08 , G06F1/10 , G06F1/06 , H04L12/64
CPC分类号： H03L7/08 , G06F1/06 , G06F1/10 , H04L12/6418
摘要： Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready.
摘要翻译：本文提供了用于在时钟分配芯片或系统中准备的系统的装置和方法。在某些配置中，通信系统包括具有分频器和相位控制电路以提供输出时钟信号的时钟产生电路。通信系统还包括系统就绪电路，以提供指示所有输出时钟信号是否准备就绪的系统就绪信号。

10. 发明授权

US09172381B2 Fast turn on system for a synthesized source signal 有权
标题翻译：快速打开系统的合成源信号
公开(公告)号：US09172381B2
公开(公告)日：2015-10-27
申请号：US13833324
申请日：2013-03-15
申请人： Hittite Microwave Corporation
发明人： Mark M. Cloutier , Greg Bachmanek , Tolga Pamir
IPC分类号： H04J3/06 , H03L7/00 , H03F3/00
CPC分类号： H03L7/00 , H03F1/30 , H03F3/00 , H03F3/195 , H03F3/45475 , H03F3/72 , H03F2200/451 , H03F2200/453 , H03F2200/459 , H03G3/348
摘要： A fast turn on compensation system for a synthesized signal source includes a synthesized signal source coupled to a power supply and configured to generate a phase stable radio frequency (RF) output signal. A mute amplifier is coupled to the synthesized signal source and the power supply. A dummy amplifier is coupled to the mute amplifier and the power supply. A mute controller is coupled to the mute amplifier and the dummy amplifier, the mute controller is responsive to an enable signal and configured to enable the dummy amplifier and disable the mute amplifier when no RF output signal is being generated and disable the dummy amplifier and enable the mute amplifier when the RF output signal is being generated such that total power supply current delivered to the synthesized signal source and the dummy amplifier or mute amplifier is approximately constant before, during, and after enabling the mute amplifier to reduce phase disturbance of the RF output signals.
摘要翻译：用于合成信号源的快速启动补偿系统包括耦合到电源并被配置为产生相位稳定射频（RF）输出信号的合成信号源。静音放大器耦合到合成信号源和电源。虚拟放大器耦合到静音放大器和电源。静音控制器耦合到静音放大器和虚拟放大器，静音控制器响应于使能信号，并配置为使能虚拟放大器，并且在没有产生RF输出信号时禁用静音放大器，并禁用虚拟放大器并使能静音放大器当RF输出信号被产生时，使得在使能静音放大器减少RF的相位扰动之前，期间和之后传送到合成信号源和虚拟放大器或静音放大器的总电源电流几乎恒定输出信号。

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