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1. 发明授权

US11144480B2 Atomic instruction having a local scope limited to an intermediate cache level 有权
公开(公告)号：US11144480B2
公开(公告)日：2021-10-12
申请号：US15452073
申请日：2017-03-07
申请人： KALRAY
发明人： Benoit Dupont De Dinechin , Marta Rybczynska , Vincent Ray
IPC分类号： G06F12/14 , G06F9/52 , G06F9/30 , G06F12/0804 , G06F12/0811 , G06F12/0815 , G06F12/0862
摘要： The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.

2. 发明授权

US09064092B2 Extensible network-on-chip 有权
标题翻译：可扩展的片上网络
公开(公告)号：US09064092B2
公开(公告)日：2015-06-23
申请号：US13572213
申请日：2012-08-10
申请人： Michel Harrand
发明人： Michel Harrand
IPC分类号： G06F13/36 , G06F15/78
CPC分类号： G06F15/7825
摘要： An integrated circuit comprises compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes; and a network extension unit at each end of each row or column of the array, inserted in a network link between two compute nodes. The extension unit has a normal mode establishing the continuity of the network link between the two corresponding compute nodes, and an extension mode dividing the network link in two independent segments that are accessible from outside the integrated circuit.
摘要翻译：集成电路包括排列成阵列的计算节点; 圆环拓扑网络片上互连计算节点; 以及插入在两个计算节点之间的网络链路中的阵列的每行或每列的每一端的网络扩展单元。扩展单元具有建立两个对应的计算节点之间的网络链路的连续性的正常模式，以及将网络链路划分为可从集成电路外部访问的两个独立的段中的扩展模式。

3. 发明申请

US20110058569A1 NETWORK ON CHIP INPUT/OUTPUT NODES 有权
标题翻译：芯片输入/输出节点上的网络
公开(公告)号：US20110058569A1
公开(公告)日：2011-03-10
申请号：US12870382
申请日：2010-08-27
申请人： Michel Harrand
发明人： Michel Harrand
IPC分类号： H04L12/28
CPC分类号： G06F13/4022 , G06F15/7825
摘要： The present invention relates to a torus network comprising a matrix of infrastructure routers, each of which is connected to two other routers belonging to the same row and to two other routers belonging to the same column; and input/output routers, each of which is connected by two internal inputs to two other routers belonging either to the same row, or to the same column, and comprising an external input for supplying the network with data. Each input/output router is devoid of queues for its internal inputs and comprises queues assigned to its external input managed by an arbiter which is configured to also manage the queues of an infrastructure router connected to the input/output router.
摘要翻译：环形网络技术领域本发明涉及一种环面网络，其包括基础设施路由器的矩阵，每个路由器连接到属于同一行的另外两个路由器和属于同一列的另外两个路由器; 以及输入/输出路由器，每个路由器通过两个内部输入连接到属于同一行或同一列的另外两个路由器，并且包括用于向网络提供数据的外部输入。每个输入/输出路由器缺少其内部输入的队列，并且包括分配给由仲裁器管理的外部输入的队列，该仲裁器被配置为还管理连接到输入/输出路由器的基础设施路由器的队列。

4. 发明授权

US11489544B2 Fast CRC computation circuit using an on-the-fly reconfigurable generator polynomial 有权
公开(公告)号：US11489544B2
公开(公告)日：2022-11-01
申请号：US17217640
申请日：2021-03-30
申请人： Kalray
发明人： Nicolas Brunie
IPC分类号： H03M13/09
摘要： A circuit for generating an N-bit cyclic redundancy code of a k-bit digit d, the code based on a reconfigurable generator polynomial P of degree N, the circuit including a dynamic table comprising a multiplication sub-table storing products resulting from multiplication by the polynomial P of each element definable over k bits, in the order of the scalar values of the k-bit elements; a division sub-table storing quotients resulting from Euclidean division by the polynomial P of each k-bit element shifted by N bits to the left, in the order of the scalar values of the k-bit elements; and a group of first multiplexers, each multiplexer connected to be indexed by a respective cell of the division table to transmit the contents of a corresponding cell of the multiplication table to an output of the dynamic table, of same rank as the respective cell of the division table.

5. 发明授权

US11294627B2 Floating point dot-product operator with correct rounding 有权
公开(公告)号：US11294627B2
公开(公告)日：2022-04-05
申请号：US16946526
申请日：2020-06-25
申请人： Kalray
发明人： Nicolas Brunie
IPC分类号： G06F7/487 , G06F7/499 , H03M7/24
摘要： The disclosure relates to a hardware operator for dot-product computation, comprising a plurality of multipliers each receiving two multiplicands in the form of floating-point numbers encoded in a first precision format; an alignment circuit associated with each multiplier, configured to, based on the exponents of the corresponding multiplicands, convert the result of the multiplication into a respective fixed-point number having a sufficient number of bits to cover the full dynamic range of the multiplication; and a multi-adder configured to add without loss the fixed-point numbers provided by the multipliers, providing a sum in the form of a fixed-point number.

6. 发明授权

US10175989B2 VLIW type instruction packet structure and processor suitable for processing such an instruction packet 有权
公开(公告)号：US10175989B2
公开(公告)日：2019-01-08
申请号：US15312961
申请日：2015-04-27
申请人： KALRAY
发明人： Renaud Ayrignac , Vincent Ray , Benoît Dupont De Dinechin
IPC分类号： G06F8/41 , G06F9/30 , G06F9/38
摘要： A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.

7. 发明授权

US08503466B2 Network on chip input/output nodes 有权
标题翻译：网络片上输入/输出节点
公开(公告)号：US08503466B2
公开(公告)日：2013-08-06
申请号：US12870382
申请日：2010-08-27
申请人： Michel Harrand
发明人： Michel Harrand
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： G06F13/4022 , G06F15/7825
摘要： The present invention relates to a torus network comprising a matrix of infrastructure routers, each of which is connected to two other routers belonging to the same row and to two other routers belonging to the same column; and input/output routers, each of which is connected by two internal inputs to two other routers belonging either to the same row, or to the same column, and comprising an external input for supplying the network with data. Each input/output router is devoid of queues for its internal inputs and comprises queues assigned to its external input managed by an arbiter which is configured to also manage the queues of an infrastructure router connected to the input/output router.
摘要翻译：环形网络技术领域本发明涉及一种环面网络，其包括基础设施路由器的矩阵，每个路由器连接到属于同一行的另外两个路由器和属于同一列的另外两个路由器; 以及输入/输出路由器，每个路由器通过两个内部输入连接到属于同一行或同一列的另外两个路由器，并且包括用于向网络提供数据的外部输入。每个输入/输出路由器缺少其内部输入的队列，并且包括分配给由仲裁器管理的外部输入的队列，该仲裁器被配置为还管理连接到输入/输出路由器的基础设施路由器的队列。

8. 发明申请

US20130054811A1 EXTENSIBLE NETWORK-ON-CHIP 有权
标题翻译：可扩展的网络芯片
公开(公告)号：US20130054811A1
公开(公告)日：2013-02-28
申请号：US13572213
申请日：2012-08-10
申请人： Michel HARRAND
发明人： Michel HARRAND
IPC分类号： G06F15/173
CPC分类号： G06F15/7825
摘要： An integrated circuit comprises compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes; and a network extension unit at each end of each row or column of the array, inserted in a network link between two compute nodes. The extension unit has a normal mode establishing the continuity of the network link between the two corresponding compute nodes, and an extension mode dividing the network link in two independent segments that are accessible from outside the integrated circuit.
摘要翻译：集成电路包括排列成阵列的计算节点; 圆环拓扑网络片上互连计算节点; 以及插入在两个计算节点之间的网络链路中的阵列的每一行或每列的每一端的网络扩展单元。扩展单元具有建立两个对应的计算节点之间的网络链路的连续性的正常模式，以及将网络链路划分为可从集成电路外部访问的两个独立的段中的扩展模式。

9. 发明申请

US20210200904A1 PROCESSOR WITH A CONFIGURABLE DISTRIBUTION OF PRIVILEGED RESOURCES AND EXCEPTIONS BETWEEN PROTECTION RINGS 有权
公开(公告)号：US20210200904A1
公开(公告)日：2021-07-01
申请号：US17139662
申请日：2020-12-31
申请人： Kalray
发明人： Pierre GUIRONNET DE MASSAS , Vincent RAY , Benoit DUPONT DE DINECHIN
IPC分类号： G06F21/71
摘要： A processor having a plurality of protection rings and comprising a protection ring management system in which the attributions of exceptions or privileged resources to protection rings are defined by a programmable table.

10. 发明授权

US09766951B2 Hardware synchronization barrier between processing units 有权
公开(公告)号：US09766951B2
公开(公告)日：2017-09-19
申请号：US14721695
申请日：2015-05-26
申请人： KALRAY
发明人： Thomas Champseix , Benoît Dupont De Dinechin , Pierre Guironnet De Massas
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F15/00 , G06F15/76 , G06F9/52 , G06F9/54
CPC分类号： G06F9/522 , G06F9/52 , G06F9/54
摘要： A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.

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