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1. 发明授权

US08970262B2 Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices 有权
标题翻译：具有第一半导体器件和多个第二半导体器件的半导体器件布置
公开(公告)号：US08970262B2
公开(公告)日：2015-03-03
申请号：US13978373
申请日：2012-01-09
申请人： Rolf Weis , Franz Hirler , Martin Feldtkeller , Gerald Deboy , Matthias Stecher , Armin Willmeroth
发明人： Rolf Weis , Franz Hirler , Martin Feldtkeller , Gerald Deboy , Matthias Stecher , Armin Willmeroth
IPC分类号： H03B1/00 , H03K3/00 , H01L27/088 , H03K17/06 , H01L21/8234 , H01L29/78 , H01L29/423 , H01L27/098 , H01L29/06
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0623 , H01L27/0629 , H01L27/0727 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L27/098 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/4236 , H01L29/4238 , H01L29/78 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/7838 , H03K17/06
摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个晶体管的控制端子连接到第一半导体器件的负载端子之一。

2. 发明授权

US08901752B2 Tuning the efficiency in the transmission of radio-frequency signals using micro-bumps 有权
标题翻译：调整使用微型突起传播射频信号的效率
公开(公告)号：US08901752B2
公开(公告)日：2014-12-02
申请号：US13841577
申请日：2013-03-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Cheng-Hung Lee , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/60 , H01L23/66 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2223/6677 , H01L2224/0401 , H01L2224/05023 , H01L2224/05073 , H01L2224/05147 , H01L2224/05567 , H01L2224/05568 , H01L2224/05655 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/17517 , H01L2224/81455 , H01L2225/06513 , H01L2924/00014 , H01L2924/01029 , H01L2924/13091 , H01L2924/14 , H01L2924/1421 , H01L2924/15192 , H01L2924/15311 , H01L2924/19104 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2224/131 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.
摘要翻译：一种器件包括：裸片，包括主电路和耦合到主电路的第一焊盘。包括第二垫的工件被结合到模具。第一多个微凸块在第一和第二焊盘之间串联电耦合。多个微型凸块中的每一个包括连接模具的第一端和连接工件的第二端。微凸块与模具和工件结合。第二焊盘电耦合到微凸起。

3. 发明授权

US08896060B2 Trench power MOSFET 有权
标题翻译：沟槽功率MOSFET
公开(公告)号：US08896060B2
公开(公告)日：2014-11-25
申请号：US13486681
申请日：2012-06-01
申请人： Chun-Wai Ng , Hsueh-Liang Chou , Ruey-Hsin Liu , Po-Chih Su
发明人： Chun-Wai Ng , Hsueh-Liang Chou , Ruey-Hsin Liu , Po-Chih Su
IPC分类号： H01L29/78
CPC分类号： H01L29/66734 , H01L21/02233 , H01L21/26586 , H01L21/266 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4916 , H01L29/495 , H01L29/66727 , H01L29/7813
摘要： A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
摘要翻译：器件包括第一导电类型的半导体区域，延伸到半导体区域中的沟槽以及沟槽中的导电场板。第一电介质层将场板的底部和侧壁与半导体区域分开。主栅极设置在沟槽中并与场板重叠。第二介电层设置在主栅极和场板之间并将其分离。第一导电类型的掺杂漏极（DD）区域在第二介电层下面，其中主栅极的边缘部分与DD区域重叠。身体区域包括与主门的一部分相同水平的第一部分和与DD区域相同水平并与其接触的第二部分，其中身体区域具有与第一导电性相反的第二导电类型类型。

4. 发明授权

US08890232B2 Methods and apparatus for non-volatile memory cells with increased programming efficiency 有权
公开(公告)号：US08890232B2
公开(公告)日：2014-11-18
申请号：US14176968
申请日：2014-02-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yong-Shiuan Tsair , Wen-Ting Chu , Po-Wei Liu , Wen-Tuo Huang , Yu-Hsiang Yang , Chieh-Fei Chiu , Yu-Ling Hsu
IPC分类号： H01L29/788 , H01L27/115 , H01L29/423 , H01L21/28
CPC分类号： H01L21/28273 , H01L27/11517 , H01L29/42328 , H01L29/7881
摘要： Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

5. 发明授权

US08889461B2 CIS image sensors with epitaxy layers and methods for forming the same 有权
标题翻译：具有外延层的CIS图像传感器及其形成方法
公开(公告)号：US08889461B2
公开(公告)日：2014-11-18
申请号：US13620322
申请日：2012-09-14
申请人： Shiu-Ko JangJian , Min Hao Hong , Kei-Wei Chen , Chih-Cherng Jeng
发明人： Shiu-Ko JangJian , Min Hao Hong , Kei-Wei Chen , Chih-Cherng Jeng
IPC分类号： H01L31/113 , H01L27/146
CPC分类号： H01L27/14645 , H01L27/14612 , H01L27/14616 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14636 , H01L27/1464 , H01L27/14689 , H01L29/16 , H01L31/028 , H01L31/103 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric.
摘要翻译：一种方法包括执行第一外延以生长第一导电类型的第一外延层，以及执行第二外延以在第一外延层上生长与第一导电类型相反的第二导电类型的第二外延层。第一和第二外延层形成二极管。该方法还包括在第一外延层上形成栅极电介质，在栅极电介质上方形成栅电极，以及注入第一外延层和第二外延层的顶部部分，以形成与栅极电介质相邻的源极/漏极区域。

6. 发明授权

US08878281B2 Methods and apparatus for non-volatile memory cells 有权
标题翻译：用于非易失性记忆体的方法和装置
公开(公告)号：US08878281B2
公开(公告)日：2014-11-04
申请号：US13478406
申请日：2012-05-23
申请人： Chung-Jen Huang , Hung-Yueh Chen
发明人： Chung-Jen Huang , Hung-Yueh Chen
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L29/42328 , H01L29/7881
摘要： Methods and apparatus for non-volatile memory cells. A memory cell includes a floating gate formed over a substrate with a tunneling dielectric over an upper surface of the floating gate and an erase gate over the tunneling dielectric. Sidewall dielectrics enclose the tunneling dielectric. Assist gates and coupling gates are formed on either side of the memory cell and are spaced from the floating gate of the memory cell by the sidewall dielectrics. Methods for forming memory cells include depositing a floating gate over a dielectric layer over a semiconductor substrate, depositing a tunneling dielectric over the floating gate, depositing an erase gate over the tunneling dielectric, patterning the erase gate, tunneling dielectric and floating gate to form memory cells having vertical sides, and depositing sidewall dielectrics on the vertical sides of the memory cells to seal the tunneling dielectrics. Additional steps are performed to complete the cells.
摘要翻译：用于非易失性记忆体的方法和装置。存储单元包括在衬底上形成的浮动栅极，在浮置栅极的上表面上具有隧穿电介质，以及在隧道电介质上方的擦除栅极。侧壁电介质包围隧道电介质。辅助栅极和耦合栅极形成在存储单元的任一侧上，并且通过侧壁电介质与存储器单元的浮动栅极间隔开。用于形成存储器单元的方法包括在半导体衬底上的电介质层上沉积浮置栅极，在浮置栅极上沉积隧道电介质，在隧道电介质上沉积擦除栅极，图案化擦除栅极，隧穿电介质和浮动栅极以形成存储器电池具有垂直边，并且在存储单元的垂直侧上沉积侧壁电介质以密封隧道电介质。执行附加步骤以完成单元。

7. 发明授权

US08877614B2 Spacer for semiconductor structure contact 有权
标题翻译：用于半导体结构接触的间隔物
公开(公告)号：US08877614B2
公开(公告)日：2014-11-04
申请号：US13272875
申请日：2011-10-13
申请人： Chun-Hung Ko , Jyh-Huei Chen , Ming-Jie Huang
发明人： Chun-Hung Ko , Jyh-Huei Chen , Ming-Jie Huang
IPC分类号： H01L29/78 , H01L21/336 , H01L21/20 , H01L21/768 , H01L29/66
CPC分类号： H01L21/76834 , H01L21/76897 , H01L29/66628 , H01L29/66636
摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.
摘要翻译：一个实施例是半导体结构。半导体结构包括外延区域，栅极结构，接触间隔物和蚀刻停止层。外延区域在衬底中。外延区的顶表面从衬底的顶表面升高，并且外延区具有在衬底的顶表面和外延区的顶表面之间的刻面。栅极结构在衬底上。接触间隔物横向在外延区域的小面和栅极结构之间。蚀刻停止层在每个接触间隔物和外延区域的顶表面之上并相邻。接触间隔物的蚀刻选择性与蚀刻停止层的蚀刻选择性的比率等于或小于3:1。

8. 发明授权

US08860151B2 Semiconductor device having a spacer and a liner overlying a sidewall of a gate structure and method of forming the same 有权
标题翻译：具有间隔物和覆盖栅极结构的侧壁的衬垫的半导体器件及其形成方法
公开(公告)号：US08860151B2
公开(公告)日：2014-10-14
申请号：US13782072
申请日：2013-03-01
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Sheng-Ching Chen , Kuang-Hsin Chen , Bor-Zen Tien , Tzong-Sheng Chang
IPC分类号： H01L21/02 , H01L29/78 , H01L21/76
CPC分类号： H01L29/78 , H01L21/76 , H01L29/66545
摘要： A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a top surface of the substrate.
摘要翻译：半导体器件包括在衬底上的栅极结构。该器件还包括衬底中的隔离特征并且与栅极结构的边缘相邻。该装置还包括覆盖栅极结构的侧壁的间隔物。间隔物的底部低于衬底的顶表面。

9. 发明授权

US08853801B2 MEMS devices and methods of forming the same 有权
标题翻译： MEMS器件及其形成方法
公开(公告)号：US08853801B2
公开(公告)日：2014-10-07
申请号：US13450728
申请日：2012-04-19
申请人： Shang-Ying Tsai , Jung-Huei Peng , Hsin-Ting Huang , Yao-Te Huang , Lung Yuan Pan , Hung-Hua Lin
发明人： Shang-Ying Tsai , Jung-Huei Peng , Hsin-Ting Huang , Yao-Te Huang , Lung Yuan Pan , Hung-Hua Lin
IPC分类号： H01L29/788
CPC分类号： B81B7/0006 , B81B2203/0307 , B81C1/00039 , B81C1/00134 , B81C1/00166 , B81C1/00341 , G01P15/0802 , G01P15/125 , G01P2015/0871 , H01G5/18 , H01L28/60
摘要： A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
摘要翻译：器件包括衬底，衬底上的布线导线，路由导线上的电介质层以及介电层上的蚀刻停止层。微机电系统（MEMS）器件具有超过蚀刻停止层的部分。接触插塞穿过蚀刻停止层和电介质层。接触插头将MEMS器件的部分连接到布线导线。保护环设置在蚀刻停止层上方和MEMS器件下方，其中护送环环绕接触插塞。

10. 发明授权

US08853071B2 Electrical connectors and methods for forming the same 有权
标题翻译：电连接器及其形成方法
公开(公告)号：US08853071B2
公开(公告)日：2014-10-07
申请号：US13789899
申请日：2013-03-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chun-Chieh Wang , Hung-Jui Kuo , Chung-Shi Liu
IPC分类号： H01L21/70 , H01L23/00
CPC分类号： H01L24/11 , H01L21/0274 , H01L23/3192 , H01L24/13 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/1146 , H01L2224/11472 , H01L2224/11902 , H01L2224/13005 , H01L2224/13006 , H01L2224/13007 , H01L2224/13012 , H01L2224/13014 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2924/00014 , H01L2924/00012 , H01L2924/206 , H01L2924/207 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/01029
摘要： A method includes coating a photo resist over an Under-Bump Metallurgy (UBM) layer and exposing the photo resist. In the step of exposing, a light amount reaching a bottom of the photo resist is less than about 5 percent of a light amount reaching a top surface of the photo resist. The method further includes developing the photo resist to form an opening in the photo resist. A portion of the UBM layer is exposed through the opening. The opening has a bottom lateral dimension greater than a top lateral dimension. An electrical connector is formed in the opening, wherein the electrical connector is non-reflowable.
摘要翻译：一种方法包括在低于Bump冶金（UBM）层上涂覆光致抗蚀剂并曝光光致抗蚀剂。在曝光的步骤中，到达光致抗蚀剂底部的光量小于到达光致抗蚀剂顶表面的光量的约5％。该方法还包括显影光致抗蚀剂以在光致抗蚀剂中形成开口。 UBM层的一部分通过开口露出。开口具有大于顶部横向尺寸的底部横向尺寸。电连接器形成在开口中，其中电连接器是不可回流的。

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