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    • 2. 发明授权
    • Taxonomy-driven lumping for sequence mining
    • 用于序列挖掘的分类学驱动的块
    • US08346686B2
    • 2013-01-01
    • US12534706
    • 2009-08-03
    • Aristides GionisFrancesco BonchiDebora Donato
    • Aristides GionisFrancesco BonchiDebora Donato
    • G06F15/18
    • G06N99/005
    • Methods and apparatus are described for modeling sequences of events with Markov models whose states correspond to nodes in a provided taxonomy. Each state represents the events in the subtree under the corresponding node. By lumping observed events into states that correspond to internal nodes in the taxonomy, more compact models are achieved that are easier to understand and visualize, at the expense of a decrease in the data likelihood. The decision for selecting the best model is taken on the basis of two competing goals: maximizing the data likelihood, while minimizing the model complexity (i.e., the number of states).
    • 描述了使用马尔可夫模型建模事件序列的方法和装置,其状态对应于所提供的分类法中的节点。 每个状态表示相应节点下的子树中的事件。 通过将观察到的事件结合到与分类学中的内部节点对应的状态,实现更容易理解和可视化的更紧凑的模型,牺牲了数据可能性的降低。 选择最佳模型的决定是基于两个竞争目标:最大化数据可能性,同时最小化模型复杂度(即状态数)。
    • 6. 发明授权
    • Early logic mapper during FPGA synthesis
    • FPGA合成期间的早期逻辑映射器
    • US08166436B1
    • 2012-04-24
    • US12430757
    • 2009-04-27
    • Gregg William Baeckler
    • Gregg William Baeckler
    • G06F17/50
    • G06F17/5054
    • Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for PLDs. The method of the algorithm involves performing a high level synthesis of the logic design to generate a netlist, performing a multilevel synthesis on the netlist to generate a gate implementation of the netlist, and performing technology mapping on the gate implementation to map the gate implementation to actual resources on the target device. During the high level synthesis of the logic design into the netlist, technology mapping is performed on a selected portion of the logic design.
    • 编程软件定义了一种在技术映射之前在合成流程过程早期提供逻辑设计的功率,面积和频率可预测性的算法,而不会降低PLD设计实现的功率,速度或面积。 该算法的方法涉及执行逻辑设计的高级合成以生成网表,在网表上执行多级综合以产生网表的门实现,以及在门实现上执行技术映射以将门实现映射到 目标设备上的实际资源。 在逻辑设计的高级合成到网表中,在逻辑设计的选定部分执行技术映射。
    • 7. 发明授权
    • Transceiver link bit error rate prediction
    • 收发器链路误码率预测
    • US08103469B1
    • 2012-01-24
    • US11297611
    • 2005-12-07
    • San WongDaniel Tun Lai ChowGeping Liu
    • San WongDaniel Tun Lai ChowGeping Liu
    • G01R13/00G01R13/02G01R29/26
    • G01R31/3171G01R31/31709
    • A method for predicting a predetermined bit error rate for an actual data transmission from a transmitter to a target receiver over an actual backplane link is disclosed. The method involves defining a simulated backplane corresponding to an actual backplane link intended to be used for data transmission between a transmitter and a target receiver. Once the simulated backplane is defined, a data transmission from the transmitter to the receiver is simulated and captured across the simulated backplane. A waveform simulation of the data transmission over the simulated backplane is then generated. The waveform simulation takes into account characteristics of the simulated backplane and the target receiver. From the waveform simulation, a total jitter for a predetermined bit error rate for the data transmission is extrapolated.
    • 公开了一种用于预测通过实际背板链路从发射机到目标接收机的实际数据传输的预定比特误码率的方法。 该方法涉及定义对应于旨在用于发射机和目标接收机之间的数据传输的实际背板链路的模拟背板。 一旦模拟背板被定义,从模拟背板模拟和捕获从发射机到接收机的数据传输。 然后生成模拟背板上的数据传输的波形模拟。 波形仿真考虑了仿真背板和目标接收机的特性。 从波形模拟中,外推了用于数据传输的预定误码率的总抖动。