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1. 发明申请

US20220334982A1 APPARATUS AND METHOD FOR MEMORY MANAGEMENT IN A GRAPHICS PROCESSING ENVIRONMENT 有权
公开(公告)号：US20220334982A1
公开(公告)日：2022-10-20
申请号：US17827556
申请日：2022-05-27
申请人： NIRANJAN L. COORAY , ABHISHEK R. APPU , ALTUG KOKER , JOYDEEP RAY , BALAJI VEMBU , PATTABHIRAMAN K , DAVID PUFFER , DAVID J. COWPERTHWAITE , RAJESH M. SANKARAN , SATYESHWAR SINGH , SAMEER KP , ANKUR N. SHAH , KUN TIAN
发明人： NIRANJAN L. COORAY , ABHISHEK R. APPU , ALTUG KOKER , JOYDEEP RAY , BALAJI VEMBU , PATTABHIRAMAN K , DAVID PUFFER , DAVID J. COWPERTHWAITE , RAJESH M. SANKARAN , SATYESHWAR SINGH , SAMEER KP , ANKUR N. SHAH , KUN TIAN
IPC分类号： G06F13/16 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/0802 , G06F13/40
摘要： An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

2. 发明申请

US20190303334A1 System, Apparatus And Method For Multi-Die Distributed Memory Mapped Input/Output Support 审中-公开
公开(公告)号：US20190303334A1
公开(公告)日：2019-10-03
申请号：US16447025
申请日：2019-06-20
申请人： Bryan R. White , Aravindh Anantaraman , Ankur Shah , Altug Koker , David Puffer , Aditya Navale
发明人： Bryan R. White , Aravindh Anantaraman , Ankur Shah , Altug Koker , David Puffer , Aditya Navale
IPC分类号： G06F13/40 , G06F13/42 , G06T1/20
摘要： In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

3. 发明申请

US20180301120A1 System, Apparatus And Method For Reducing Voltage Swing On An Interconnect 审中-公开
公开(公告)号：US20180301120A1
公开(公告)日：2018-10-18
申请号：US15488673
申请日：2017-04-17
申请人： Anupama A. Thaploo , Jaydeep P. Kulkarni , Bhushan M. Borole , Abhishek R. Appu , Altug Koker , Kamal Sinha , Wenyin Fu
发明人： Anupama A. Thaploo , Jaydeep P. Kulkarni , Bhushan M. Borole , Abhishek R. Appu , Altug Koker , Kamal Sinha , Wenyin Fu
IPC分类号： G09G5/36
摘要： In an embodiment, an apparatus includes: a repeater to receive an input signal at an input node and output an output signal at an output node; a dynamic header device coupled between the repeater and a supply voltage node; and a feedback device coupled between the output node and the dynamic header device to dynamically control the dynamic header device based at least in part on the output signal. Other embodiments are described and claimed.

4. 发明申请

US20180301119A1 System, Apparatus And Method For Increasing Performance In A Processor During A Voltage Ramp 审中-公开
公开(公告)号：US20180301119A1
公开(公告)日：2018-10-18
申请号：US15488662
申请日：2017-04-17
申请人： Altug Koker , Abhishek R. Appu , Bhushan M. Borole , Wenyin Fu , Kamal Sinha , Joydeep Ray
发明人： Altug Koker , Abhishek R. Appu , Bhushan M. Borole , Wenyin Fu , Kamal Sinha , Joydeep Ray
IPC分类号： G09G5/36
CPC分类号： G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G09G5/366 , G09G2310/066 , G09G2310/08 , G09G2340/02 , G09G2360/06 , G09G2360/08 , G09G2370/022 , G09G2370/16
摘要： In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

5. 发明申请

US20180293185A1 APPARATUS AND METHOD FOR DYNAMIC PROVISIONING, QUALITY OF SERVICE, AND SCHEDULING 审中-公开
公开(公告)号：US20180293185A1
公开(公告)日：2018-10-11
申请号：US15482666
申请日：2017-04-07
申请人： BALAJI VEMBU , ALTUG KOKER , JOYDEEP RAY , ABHISHEK R. APPU , PATTABHIRAMAN K , NIRANJAN L. COORAY
发明人： BALAJI VEMBU , ALTUG KOKER , JOYDEEP RAY , ABHISHEK R. APPU , PATTABHIRAMAN K , NIRANJAN L. COORAY
IPC分类号： G06F13/16 , G06F3/06 , G06F12/0802 , G06F12/1045 , G06F13/40
摘要： An apparatus and method for dynamic provisioning and traffic control on a memory fabric. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated set of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment; and a plurality of queues associated with each VM at different levels of a memory interconnection fabric, the queues for a first VM to store memory traffic for that VM at the different levels of the memory interconnection fabric; arbitration hardware logic coupled to the plurality of queues and distributed across the different levels of the memory interconnection fabric, the arbitration hardware logic to cause memory traffic to be blocked from one or more upstream queues of the first VM upon detecting that a downstream queue associated with the first VM is full or at a specified threshold.

6. 发明申请

US20180285106A1 HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK 审中-公开
公开(公告)号：US20180285106A1
公开(公告)日：2018-10-04
申请号：US15477033
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F9/30 , G06T15/00 , G06T1/60 , G06T1/20 , G06F9/46 , G09G5/36
摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

7. 发明申请

US20150103084A1 SUPPORTING ATOMIC OPERATIONS AS POST-SYNCHRONIZATION OPERATIONS IN GRAPHICS PROCESSING ARCHITECTURES 有权
标题翻译：支持原始操作作为图形处理架构中的同步操作
公开(公告)号：US20150103084A1
公开(公告)日：2015-04-16
申请号：US14050626
申请日：2013-10-10
申请人： Hema C. Nalluri , Aditya Navale , Altug Koker
发明人： Hema C. Nalluri , Aditya Navale , Altug Koker
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： Methods and systems may provide for storing a set of post-synchronization operations to a graphics memory and sending a flush marker to a graphics pipeline. Additionally, the set of post-synchronization operations may be processed in response to the flush marker exiting the graphics pipeline. In one example, the set of post-synchronization operations includes one or more atomic operations. Moreover, the set of post-synchronization operations may be obtained from an inline portion of an atomics command.
摘要翻译：方法和系统可以提供将一组后同步操作存储到图形存储器并且向图形流水线发送冲洗标记。另外，可以响应于离开图形管线的冲洗标记来处理该后同步操作的集合。在一个示例中，该后同步操作集合包括一个或多个原子操作。此外，可以从原子命令的内联部分获得该后同步操作的集合。

8. 发明申请

US20150035840A1 USING GROUP PAGE FAULT DESCRIPTORS TO HANDLE CONTEXT SWITCHES AND PROCESS TERMINATIONS IN GRAPHICS PROCESSORS 有权
标题翻译：使用组页面故障描述符来处理图形处理器中的上下文开关和处理终止
公开(公告)号：US20150035840A1
公开(公告)日：2015-02-05
申请号：US13958824
申请日：2013-08-05
申请人： ALTUG Koker
发明人： ALTUG Koker
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/38 , G06F9/3861 , G06F9/542 , G06F11/073 , G06T1/60
摘要： Methods and systems may provide for detecting an end of execution of a process on a graphics processor and providing a group page fault descriptor to a page miss handler of an operating system (OS) in response to the end of execution of the process, wherein the group page fault descriptor may indicate to the page miss handler that no further page fault requests will be generated by the graphics processor until one or more outstanding page fault requests are satisfied. Additionally, a response to the group page fault descriptor may be received from the page miss handler. In one example, a process identifier is incorporated into the group page fault descriptor, wherein the process identifier is shared by the group page fault descriptor and the one or more outstanding page fault requests.
摘要翻译：响应于该过程的执行结束，方法和系统可以提供用于检测图形处理器上的进程的执行结束并将操作系统（OS）的页面错误处理程序提供给组页面错误描述符，其中，组页面错误描述符可以向页面未命中处理程序指示，直到满足一个或多个未完成页面错误请求之前，图形处理器将不会产生进一步的页面错误请求。另外，可以从页面错误处理程序接收对组页面错误描述符的响应。在一个示例中，流程标识符被合并到组页面错误描述符中，其中过程标识符由组页面错误描述符和一个或多个未完成的页面错误请求共享。

9. 发明申请

US20130031333A1 METHOD AND APPARATUS FOR TLB SHOOT-DOWN IN A HETEROGENEOUS COMPUTING SYSTEM SUPPORTING SHARED VIRTUAL MEMORY 有权
标题翻译：支持共享虚拟内存的异构计算系统中TLB SHOOT-DOWN的方法和设备
公开(公告)号：US20130031333A1
公开(公告)日：2013-01-31
申请号：US13191327
申请日：2011-07-26
申请人： Rajesh M. Sankaran , Altug Koker , Philip R. Lantz , Asit K. Mallick , James B. Crossland , Aditya Navale , Gilbert Neiger , Andrew V. Anderson
发明人： Rajesh M. Sankaran , Altug Koker , Philip R. Lantz , Asit K. Mallick , James B. Crossland , Aditya Navale , Gilbert Neiger , Andrew V. Anderson
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1081 , G06F2212/1016 , G06F2212/1048 , G06F2212/303 , G06F2212/682 , G06F2212/683
摘要： Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.
摘要翻译：公开了用于在多核系统中共享虚拟存储器的异构设备的有效TLB（转换后备缓冲器）击穿的方法和装置。用于有效的TLB击倒的装置的实施例可以包括用于存储虚拟地址转换条目的TLB和与TLB耦合的存储器管理单元，以维护对应于虚拟地址转换条目的PASID（进程地址空间标识符）状态条目。 PASID状态条目可以包括活动参考状态和惰性无效状态。响应于从多核系统中的设备接收到PASID状态更新请求并且读取PASID状态条目的惰性无效状态，存储器管理单元可执行PASID状态条目的原子修改。存储器管理单元可以在响应于相应的惰性无效化状态的激活之前向设备发送PASID状态更新响应以同步TLB条目。

10. 发明授权

US10649956B2 Engine to enable high speed context switching via on-die storage 有权
公开(公告)号：US10649956B2
公开(公告)日：2020-05-12
申请号：US15477027
申请日：2017-04-01
申请人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
发明人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
IPC分类号： G06F16/13 , G06F9/38 , G06F9/30 , G06F16/11 , G06F16/172 , G06F9/46 , G06F12/1036 , G06F12/1045 , G06F12/0831
摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

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