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1. 发明申请

US20220334982A1 APPARATUS AND METHOD FOR MEMORY MANAGEMENT IN A GRAPHICS PROCESSING ENVIRONMENT 有权
公开(公告)号：US20220334982A1
公开(公告)日：2022-10-20
申请号：US17827556
申请日：2022-05-27
申请人： NIRANJAN L. COORAY , ABHISHEK R. APPU , ALTUG KOKER , JOYDEEP RAY , BALAJI VEMBU , PATTABHIRAMAN K , DAVID PUFFER , DAVID J. COWPERTHWAITE , RAJESH M. SANKARAN , SATYESHWAR SINGH , SAMEER KP , ANKUR N. SHAH , KUN TIAN
发明人： NIRANJAN L. COORAY , ABHISHEK R. APPU , ALTUG KOKER , JOYDEEP RAY , BALAJI VEMBU , PATTABHIRAMAN K , DAVID PUFFER , DAVID J. COWPERTHWAITE , RAJESH M. SANKARAN , SATYESHWAR SINGH , SAMEER KP , ANKUR N. SHAH , KUN TIAN
IPC分类号： G06F13/16 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/0802 , G06F13/40
摘要： An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

2. 发明申请

US20220269433A1 SYSTEM, METHOD AND APPARATUS FOR PEER-TO-PEER COMMUNICATION 有权
公开(公告)号：US20220269433A1
公开(公告)日：2022-08-25
申请号：US17682015
申请日：2022-02-28
申请人： Rahul Pal , Susanne M. Balle , David Puffer , Nagabhushan Chitlur
发明人： Rahul Pal , Susanne M. Balle , David Puffer , Nagabhushan Chitlur
IPC分类号： G06F3/06
摘要： In an embodiment, an apparatus includes: a first downstream port to couple to a first peer device; a second downstream port to couple to a second peer device; and a peer-to-peer (PTP) circuit to receive a memory access request from the first peer device, the memory access request having a target associated with the second peer device, where the PTP circuit is to convert the memory access request from a coherent protocol to a memory protocol and send the converted memory access request to the second peer device. Other embodiments are described and claimed.

3. 发明申请

US20210042254A1 ACCELERATOR CONTROLLER HUB 有权
公开(公告)号：US20210042254A1
公开(公告)日：2021-02-11
申请号：US17083200
申请日：2020-10-28
申请人： Pratik Marolia , Andrew Herdrich , Rajesh Sankaran , Rahul Pal , David Puffer , Sayantan Sur , Ajaya Durg
发明人： Pratik Marolia , Andrew Herdrich , Rajesh Sankaran , Rahul Pal , David Puffer , Sayantan Sur , Ajaya Durg
IPC分类号： G06F13/40 , G06F13/42
摘要： Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

4. 发明申请

US20190303334A1 System, Apparatus And Method For Multi-Die Distributed Memory Mapped Input/Output Support 审中-公开
公开(公告)号：US20190303334A1
公开(公告)日：2019-10-03
申请号：US16447025
申请日：2019-06-20
申请人： Bryan R. White , Aravindh Anantaraman , Ankur Shah , Altug Koker , David Puffer , Aditya Navale
发明人： Bryan R. White , Aravindh Anantaraman , Ankur Shah , Altug Koker , David Puffer , Aditya Navale
IPC分类号： G06F13/40 , G06F13/42 , G06T1/20
摘要： In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

5. 发明申请

US20180285106A1 HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK 审中-公开
公开(公告)号：US20180285106A1
公开(公告)日：2018-10-04
申请号：US15477033
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F9/30 , G06T15/00 , G06T1/60 , G06T1/20 , G06F9/46 , G09G5/36
摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

6. 发明申请

US20140122916A1 REDUCING THE OVERHEAD ASSOCIATED WITH FREQUENCY CHANGES IN PROCESSORS 审中-公开
标题翻译：减少与处理器中频率变化相关的OVERHEAD
公开(公告)号：US20140122916A1
公开(公告)日：2014-05-01
申请号：US13664511
申请日：2012-10-31
申请人： Guadalupe J. Garcia , Lakshminarayan K. Jagannathan , David Puffer
发明人： Guadalupe J. Garcia , Lakshminarayan K. Jagannathan , David Puffer
IPC分类号： G06F1/08
CPC分类号： G06F1/08 , G06F1/324 , Y02D10/126
摘要： In many cases, processors may change frequency sufficiently often to result in significant performance and power consumption losses. These performance and power consumption losses may be mitigated by changing the frequency using a squashing technique rather than using a phase locked loop technique. The squashing technique involves simply eliminated clock pulses to reduce the frequency. This can be done more quickly, resulting in less overhead in some cases.
摘要翻译：在许多情况下，处理器可能会频繁地频繁地改变频率，从而导致显着的性能和功耗损失。这些性能和功耗损失可以通过使用压扁技术改变频率而不是使用锁相环技术来减轻。挤压技术简单地消除了时钟脉冲以降低频率。这可以更快地完成，在某些情况下导致更少的开销。

7. 发明申请

US20120331321A1 Processor Core with Higher Performance Burst Operation with Lower Power Dissipation Sustained Workload Mode 有权
标题翻译：处理器核心，具有更高性能突发操作，功耗更低，持续工作负载模式
公开(公告)号：US20120331321A1
公开(公告)日：2012-12-27
申请号：US13169182
申请日：2011-06-27
申请人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
发明人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/3296 , G09G5/363 , G09G2330/021 , G09G2360/08 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： A processor may operate at a first frequency level for a first time interval. The processor automatically may transition to a sleep state from the first frequency level after the first time interval. Then the processor automatically transitions from the sleep state to the first frequency level after a second time interval. As a result the processor may operate at a reduced power consumption and higher performance.
摘要翻译：处理器可以在第一时间间隔的第一频率级别操作。处理器自动地可以在第一时间间隔之后从第一频率电平转换到睡眠状态。然后处理器在第二时间间隔后自动从休眠状态转换到第一频率级。因此，处理器可以以降低的功率消耗和更高的性能来操作。

8. 发明申请

US20050243096A1 Memory controller hub interface 有权
标题翻译：内存控制器集线器接口
公开(公告)号：US20050243096A1
公开(公告)日：2005-11-03
申请号：US11174662
申请日：2005-07-06
申请人： Brian Possley , David Puffer , Kurt Robinson , Ray Askew , James Chapple , Thomas Dever
发明人： Brian Possley , David Puffer , Kurt Robinson , Ray Askew , James Chapple , Thomas Dever
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06F3/14 , G06T1/20 , G09G5/001
摘要： A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.
摘要翻译：存储器控制器集线器包括适于对数据执行图形操作的图形子系统，以及适于选择性地通过电连接器将图形子系统耦合到本地存储器并且通过电连接器将存储器控制器集线器耦合到图形控制器的接口电路。

9. 发明申请

US20050144341A1 Buffer management via non-data symbol processing for a point to point link 审中-公开
标题翻译：通过点对点链接的非数据符号处理进行缓冲管理
公开(公告)号：US20050144341A1
公开(公告)日：2005-06-30
申请号：US10750013
申请日：2003-12-31
申请人： Daren Schmidt , David Puffer , Sarath Kotamreddy , Lyonel Renaud
发明人： Daren Schmidt , David Puffer , Sarath Kotamreddy , Lyonel Renaud
IPC分类号： G06F5/10 , G06F5/14 , G06F3/00
CPC分类号： G06F5/14
摘要： A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence that has been inserted into a data sequence by the second device. The symbols are loaded into a buffer. The data sequence and some of the non-data sequence is unloaded from the buffer, according to a changing unload pointer. To prevent overflow of the buffer, and in response to detecting the non-data sequence, the unload pointer is changed by more than one entry so that a non-data symbol of the non-data sequence as loaded in the buffer is skipped while unloading from the buffer. In another embodiment, to prevent underflow of the buffer, the unload pointer is stalled at an entry of the buffer that contains a non-data symbol while unloading. Other embodiments are also described and claimed.
摘要翻译：在第一集成电路（IC）装置中接收多个符号，其中这些符号已由第二IC器件传输并通过串行点对点链接接收。这些符号包括已被第二设备插入到数据序列中的非数据序列。符号被加载到缓冲区。根据改变的卸载指针，数据序列和一些非数据序列从缓冲区中卸载。为了防止缓冲器的溢出，并且响应于检测到非数据序列，卸载指针由多个条目改变，使得在卸载期间跳过加载在缓冲器中的非数据序列的非数据符号从缓冲区。在另一个实施例中，为了防止缓冲器的下溢，卸载指针在卸载期间在包含非数据符号的缓冲器的条目处被停止。还描述和要求保护其他实施例。

10. 发明授权

US11768781B2 Apparatus and method for memory management in a graphics processing environment 有权
公开(公告)号：US11768781B2
公开(公告)日：2023-09-26
申请号：US17827556
申请日：2022-05-27
申请人： Niranjan L. Cooray , Abhishek R. Appu , Altug Koker , Joydeep Ray , Balaji Vembu , Pattabhiraman K , David Puffer , David J. Cowperthwaite , Rajesh M. Sankaran , Satyeshwar Singh , Sameer Kp , Ankur N. Shah , Kun Tian
发明人： Niranjan L. Cooray , Abhishek R. Appu , Altug Koker , Joydeep Ray , Balaji Vembu , Pattabhiraman K , David Puffer , David J. Cowperthwaite , Rajesh M. Sankaran , Satyeshwar Singh , Sameer Kp , Ankur N. Shah , Kun Tian
IPC分类号： G06F9/455 , G06F9/50 , G06F13/16 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/0802 , G06F13/40
CPC分类号： G06F13/16 , G06F12/0802 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F13/4068 , G06F2212/1024 , G06F2212/302 , G06F2212/60 , G06F2212/68
摘要： An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

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