专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08895410B2 Method of manufacturing semiconductor device and semiconductor manufacturing apparatus 有权
标题翻译：制造半导体器件和半导体制造装置的方法
公开(公告)号：US08895410B2
公开(公告)日：2014-11-25
申请号：US11991908
申请日：2005-09-13
申请人： Tadahiro Ohmi , Akinobu Teramoto , Hiroshi Akahori
发明人： Tadahiro Ohmi , Akinobu Teramoto , Hiroshi Akahori
IPC分类号： H01L21/322 , H01L21/223 , H01L21/30 , H01L29/78 , H01L29/66 , H01L21/31
CPC分类号： H01L21/3003 , B65G2201/0247 , H01L21/31 , H01L29/6659 , H01L29/7833
摘要： A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.
摘要翻译：发现晶片表面的氢终止劣化的原因是水被吸附在表面上。通过将晶片暴露于含有H 2气体的惰性气体气氛中以抑制由于水引起的氧化反应，可以改善晶片表面上的氢终止。

2. 发明授权

US08643106B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08643106B2
公开(公告)日：2014-02-04
申请号：US12308846
申请日：2007-06-21
申请人： Tadahiro Ohmi , Akinobu Teramoto , Cheng Weitao
发明人： Tadahiro Ohmi , Akinobu Teramoto , Cheng Weitao
IPC分类号： H01L27/12
CPC分类号： H01L29/78654 , H01L29/78603 , H01L29/78648
摘要： A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.
摘要翻译：通过调整支撑SOI层的硅衬底的杂质浓度，并且通过控制形成在与SOI层接触的硅衬底表面上的掩埋绝缘层的厚度来获得能够调节阈值的晶体管。

3. 发明授权

US08633395B2 Multilayer wiring board 有权
标题翻译：多层接线板
公开(公告)号：US08633395B2
公开(公告)日：2014-01-21
申请号：US12995514
申请日：2009-05-22
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
IPC分类号： H05K1/03 , H05K1/11
CPC分类号： H05K1/0218 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2223/6688 , H01L2924/0002 , H01L2924/19032 , H01L2924/3011 , H05K1/025 , H05K1/0265 , H05K3/4652 , H05K2201/0191 , H05K2201/0352 , H05K2201/0715 , H05K2201/096 , H05K2201/09618 , H05K2201/09727 , H05K2201/09972 , H01L2924/00
摘要： A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.
摘要翻译：多层布线基板100包括：布线103a和绝缘层104a，104b交替层叠的第一布线区域101和绝缘层104的厚度H2为绝缘层的厚度H1的两倍以上的第二布线区域102 在第一布线区域101中，布线103b的宽度W2是第一布线区域101中的布线的宽度W1的两倍或更多倍。第一布线区域101和第二布线区域102一体地形成在同一个板上。

4. 发明申请

US20130292700A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件和半导体器件的方法
公开(公告)号：US20130292700A1
公开(公告)日：2013-11-07
申请号：US13981048
申请日：2012-01-23
申请人： Akinobu Teramoto , Hiroshi Kambayashi , Hirokazu Ueda , Yuichiro Morozumi , Katsushige Harada , Kazuhide Hasebe , Tadahiro Ohmi
发明人： Akinobu Teramoto , Hiroshi Kambayashi , Hirokazu Ueda , Yuichiro Morozumi , Katsushige Harada , Kazuhide Hasebe , Tadahiro Ohmi
IPC分类号： H01L29/20 , H01L21/02
CPC分类号： H01L21/02274 , H01L21/02164 , H01L21/02178 , H01L21/022 , H01L21/0228 , H01L21/0254 , H01L21/28264 , H01L23/564 , H01L29/2003 , H01L29/205 , H01L29/42364 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.
摘要翻译：一种制造半导体器件的方法，该半导体器件包括构成半导体层并包括形成栅极绝缘膜的GaN（氮化镓），其中在氮化物层上形成选自SiO 2膜和Al 2 O 3膜中的至少一种膜通过使用微波等离子体形成含GaN的GaN，并且将形成的膜用作栅极绝缘膜的至少一部分。

5. 发明授权

US08405343B2 Inverter unit, integrated circuit chip, and vehicle drive apparatus 有权
标题翻译：逆变器单元，集成电路芯片和车辆驱动装置
公开(公告)号：US08405343B2
公开(公告)日：2013-03-26
申请号：US13111122
申请日：2011-05-19
申请人： Hitoshi Sumida , Akinobu Teramoto , Ken-ichi Nonaka , Toshio Naka
发明人： Hitoshi Sumida , Akinobu Teramoto , Ken-ichi Nonaka , Toshio Naka
IPC分类号： H02P27/04
CPC分类号： H02P27/06 , B60L3/003 , B60L2210/20 , H02M7/003 , Y02T10/725
摘要： A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.
摘要翻译：一个小型化，低成本的高可靠性逆变器单元。控制电路部分，用于控制包括在逆变器电路部分中的高击穿电压半导体元件的操作定时;以及第一和第二驱动和异常检测电路部分，用于根据操作时间输出用于驱动高击穿电压半导体元件的驱动信号，将逆变器电路部分的异常返回到控制电路部分形成在作为一个集成电路芯片的SOI衬底上。在集成电路芯片上，参考电位不同的电路形成区域通过电介质彼此分离。形成用于传输由电介质分离的电路形成区域之间交换的信号的多个电平移位器。

6. 发明申请

US20130032819A1 SEMICONDUCTOR TRANSISTOR 有权
标题翻译：半导体晶体管
公开(公告)号：US20130032819A1
公开(公告)日：2013-02-07
申请号：US13582229
申请日：2011-03-02
申请人： Hiroshi Kambayashi , Katsunori Ueno , Takehiko Nomura , Yoshihiro Sato , Akinobu Teramoto , Tadahiro Ohmi
发明人： Hiroshi Kambayashi , Katsunori Ueno , Takehiko Nomura , Yoshihiro Sato , Akinobu Teramoto , Tadahiro Ohmi
IPC分类号： H01L29/51
CPC分类号： H01L21/28264 , C23C16/403 , C23C16/4488 , H01L21/02178 , H01L21/02277 , H01L29/2003 , H01L29/513 , H01L29/517 , H01L29/78
摘要： The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al2O3, HfO2, ZrO2, La2O3, and Y2O3 formed on the active layer, and a second insulating film composed of SiO2 formed on the first insulating film.
摘要翻译：根据本发明的半导体晶体管包括由有源层形成的GaN基半导体和栅极绝缘膜构成的有源层。栅极绝缘膜具有包含一种或多种选自Al 2 O 3，HfO 2，ZrO 2，La 2 O 3和Y 2 O 3的化合物的第一绝缘膜和形成在第一绝缘膜上的由SiO 2构成的第二绝缘膜。

7. 发明授权

US08328928B2 Metal nanoink and process for producing the metal nanoink, and die bonding method and die bonding apparatus using the metal nanoink 有权
标题翻译：金属纳米金属和金属纳米金属的制造工艺，以及使用金属纳米金属的芯片接合方法和芯片接合装置
公开(公告)号：US08328928B2
公开(公告)日：2012-12-11
申请号：US13055747
申请日：2009-07-08
申请人： Toru Maeda , Tetsuro Tanikawa , Akinobu Teramoto , Masaaki Oda
发明人： Toru Maeda , Tetsuro Tanikawa , Akinobu Teramoto , Masaaki Oda
IPC分类号： C09D11/00 , H01B1/02
CPC分类号： B22F1/0062 , B22F2999/00 , H01L21/4867 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/81 , H01L25/50 , H01L2224/111 , H01L2224/11318 , H01L2224/1152 , H01L2224/1329 , H01L2224/13324 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/13364 , H01L2224/13369 , H01L2224/13399 , H01L2224/16 , H01L2224/75251 , H01L2224/75252 , H01L2224/75745 , H01L2224/75753 , H01L2224/81097 , H01L2224/81193 , H01L2224/81203 , H01L2224/8184 , H01L2225/06513 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01067 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12044 , B22F1/0018 , H01L2924/00014 , H01L2924/00
摘要： Metal nanoink (100) for bonding an electrode of a semiconductor die and an electrode of a substrate and/or bonding an electrode of a semiconductor die and an electrode of another semiconductor die by sintering under pressure is produced by injecting oxygen into an organic solvent (105) in the form of oxygen nanobubbles (125) or oxygen bubbles (121) either before or after metal nanoparticles (101) whose surfaces are coated with a dispersant (102) are mixed into the organic solvent (105). Bumps are formed on the electrode of the semiconductor die and the electrode of the substrate by ejecting microdroplets of the metal nanoink (100) onto the electrodes, the semiconductor die is turned upside down and overlapped in alignment over the substrate, and then, the metal nanoparticles of the bumps are sintered under pressure by pressing and heating the bumps between the electrodes. As a result, generation of voids during sintering under pressure is minimized.
摘要翻译：通过将氧气注入到有机溶剂中来制造用于将半导体管芯的电极和基板的电极接合和/或接合半导体管芯的电极和另一个半导体管芯的电极的金属纳米管（100）在其表面涂布有分散剂（102）的金属纳米颗粒（101）之前或之后，将氧纳米气泡（125）或氧气（121）的形式混合到有机溶剂（105）中。通过将金属纳米线（100）的微滴喷射到电极上，在半导体管芯的电极和基板的电极上形成凸起，将半导体管芯上下颠倒并重叠在衬底上，然后将金属通过按压和加热电极之间的凸块，在凸起的纳米颗粒被烧结。结果，在压力下烧结过程中产生的空隙被最小化。

8. 发明申请

US20120292743A1 SURFACE TREATMENT METHOD FOR ATOMICALLY FLATTENING A SILICON WAFER AND HEAT TREATMENT APPARATUS 有权
标题翻译：表面处理方法，用于原子层析硅和热处理装置
公开(公告)号：US20120292743A1
公开(公告)日：2012-11-22
申请号：US13565868
申请日：2012-08-03
申请人： Tadahiro OHMI , Akinobu TERAMOTO , Tomoyuki SUWA
发明人： Tadahiro OHMI , Akinobu TERAMOTO , Tomoyuki SUWA
IPC分类号： F27B9/00 , H01L29/06 , F26B7/00
CPC分类号： H01L21/3247 , F27B17/0025 , H01L21/02052 , H01L21/02238 , H01L21/02252 , H01L21/302 , H01L21/67017 , H01L21/67109 , H01L21/67126 , H01L21/67757
摘要： In a silicon wafer which has a surface with a plurality of terraces formed stepwise by single-atomic-layer steps, respectively, no slip line is formed.
摘要翻译：在具有分别通过单原子层阶梯逐步形成的多个台阶的表面的硅晶片中，不形成滑移线。

9. 发明授权

US08314449B2 MIS transistor and CMOS transistor 有权
标题翻译： MIS晶体管和CMOS晶体管
公开(公告)号：US08314449B2
公开(公告)日：2012-11-20
申请号：US12604015
申请日：2009-10-22
申请人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Takefumi Nishimuta , Hiroshi Miyagi , Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： H01L21/76
CPC分类号： H01L29/7851 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L29/045
摘要： A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.
摘要翻译：形成在半导体衬底上的MIS晶体管被假设为包括半导体衬底（702,910），该半导体衬底包括在主平面上的表面上具有至少两个不同晶面的突出部分（704,910B），栅极绝缘体（708 ，920B），用于覆盖构成所述突出部分的表面的所述至少两个不同晶面的每一个的至少一部分;栅电极（706,930B），包括在构成所述表面的所述至少两个不同晶面中的每一个上所述突出部分与所述至少两个不同平面夹住所述栅极绝缘体，以及形成在所述突出部分中的所述至少两个不同晶面中的每一个的单导电型扩散区域（710a，710b，910c，910d）并分别形成在栅电极的两侧。这种配置允许控制元件面积的增加和通道宽度的增加。

10. 发明申请

US20120208375A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120208375A1
公开(公告)日：2012-08-16
申请号：US13453206
申请日：2012-04-23
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto , Hiroshi Akahori , Keiichi Nii
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Akinobu Teramoto , Hiroshi Akahori , Keiichi Nii
IPC分类号： H01L21/316 , H01L21/314
CPC分类号： H01L21/3185 , H01L21/0214 , H01L21/02142 , H01L21/02164 , H01L21/02175 , H01L21/02238 , H01L21/02271 , H01L21/02301 , H01L21/30604 , H01L21/31654 , H01L21/318 , H01L29/6659
摘要： In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
摘要翻译：在形成在具有大致（110）晶面取向的硅表面上的半导体器件中，硅表面变平，使得表面Ra的算术平均偏差不大于0.15nm，优选为0.09nm，这使得能够制造高迁移率的n-MOS晶体管。通过在脱氧H 2 O或低OH密度气氛中清洗硅表面，通过在氧自由基气氛中重复自牺牲氧化物膜的沉积工艺和自牺牲氧化物膜的去除工艺来获得这种扁平化的硅表面，或通过氢或重氢强烈地终止硅表面。自牺牲氧化膜的沉积工艺可以通过各向同性氧化进行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式